Architecture >> AxiStreamDmaRingWriteIpIntegrator::rtl

Constants
DATA_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 1 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
STATUS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 1 , tKeepMode = > TKEEP_FIXED_C , tUserMode = > TUSER_FIRST_LAST_C , tDestBits = > 4 , tUserBits = > 2 , tIdBits = > 0 )
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 4 , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )

Signals
axilResetN	sl := ' 1 '
axisResetN	sl := ' 1 '
statusResetN	sl := ' 1 '
axiResetN	sl := ' 1 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axisDataMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisDataSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
axisStatusMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisStatusSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
axiReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_data	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_status	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_axi	MasterAxiIpIntegrator <Entity MasterAxiIpIntegrator>
u_dut	AxiStreamDmaRingWrite <Entity AxiStreamDmaRingWrite>

The documentation for this design unit was generated from the following file:

Constants

Signals