Architecture >> AxiStreamDmaFifo::rtl

Functions
slv	localToSlv ( r: in AxiReadDmaReqType )
AxiReadDmaReqType	localToAxiReadDmaReq ( din: in slv , valid: in sl )
slv	localToSlv ( r: in AxiReadDmaReqType )
AxiReadDmaReqType	localToAxiReadDmaReq ( din: in slv , valid: in sl )

Processes
comb	( axiRst , axilReadMaster , axilWriteMaster , r , rdAck , rdQueueData , rdQueueValid , wrAck , wrQueueAfull )
seq	( axiClk )
comb	( axiRst , axilReadMaster , axilWriteMaster , r , rdAck , rdQueueData , rdQueueValid , wrAck , wrQueueAfull )
seq	( axiClk )

Constants
BYP_SHIFT_C	boolean := true
BIT_DIFF_C	positive := AXI_BUFFER_WIDTH_G- MAX_FRAME_WIDTH_G
ADDR_WIDTH_C	positive := ite ( ( BIT_DIFF_C< = 10 ) , BIT_DIFF_C , 10 )
CASCADE_SIZE_C	positive := ite ( ( BIT_DIFF_C< = 10 ) , 1 , 2 ( BIT_DIFF_C- 10 ) )**
LOCAL_AXI_READ_DMA_READ_REQ_SIZE_C	*integer := MAX_FRAME_WIDTH_G+ ( 2 AXIS_CONFIG_G.TUSER_BITS_C ) + AXIS_CONFIG_G.TDEST_BITS_C+ AXIS_CONFIG_G.TID_BITS_C**
REG_INIT_C	RegType := ( rstCnt = > ' 0 ' , insertSof = > SOF_INSERT_G , online = > START_AFTER_RST_G , dropOnErr = > DROP_ERR_FRAME_G , baseAddr = > AXI_BASE_ADDR_G , maxSize = > toSlv ( 2 ** MAX_FRAME_WIDTH_G , 32 ) , swCache = > AXI_CACHE_G , errorCnt = > ( others = > ' 0 ' ) , rdQueueReady = > ' 0 ' , wrQueueValid = > ' 0 ' , wrQueueData = > ( others = > ' 0 ' ) , wrIndex = > ( others = > ' 0 ' ) , rdIndex = > ( others = > ' 0 ' ) , frameCnt = > ( others = > ' 0 ' ) , frameCntMax = > ( others = > ' 0 ' ) , wrReq = > AXI_WRITE_DMA_REQ_INIT_C , rdReq = > AXI_READ_DMA_REQ_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
wrAck	AxiWriteDmaAckType
rdAck	AxiReadDmaAckType
wrQueueAfull	sl
rdQueueRst	sl
rdQueueReset	sl
rdQueueValid	sl
rdQueueReady	sl
rdQueueData	slv ( LOCAL_AXI_READ_DMA_READ_REQ_SIZE_C- 1 downto 0 )

Records
RegType

Instantiations
u_ibdma	AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_obdma	AxiStreamDmaRead <Entity AxiStreamDmaRead>
u_readqueue	FifoCascade <Entity FifoCascade>
u_rdqueuereset	RstPipeline <Entity RstPipeline>
u_ibdma	AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_obdma	AxiStreamDmaRead <Entity AxiStreamDmaRead>
u_readqueue	FifoCascade <Entity FifoCascade>
u_rdqueuereset	RstPipeline <Entity RstPipeline>

The documentation for this design unit was generated from the following files:

Functions

Processes