AxiStreamDmaFifo Entity Reference

Inheritance diagram for AxiStreamDmaFifo:

Collaboration diagram for AxiStreamDmaFifo:

Entities
AxiStreamDmaFifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
START_AFTER_RST_G	sl := ' 1 '
DROP_ERR_FRAME_G	sl := ' 1 '
SOF_INSERT_G	sl := ' 1 '
PEND_THRESH_G	natural := 0
MAX_FRAME_WIDTH_G	positive := 14
AXI_BUFFER_WIDTH_G	positive := 28
AXIS_CONFIG_G	AxiStreamConfigType
AXI_BASE_ADDR_G	slv ( 63 downto 0 ) := x " 0000_0000_0000_0000 "
AXI_CONFIG_G	AxiConfigType
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 1111 "

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

---

The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaFifo.vhd
• build/SRC_VHDL/surf/AxiStreamDmaFifo.vhd