Architecture >> AxiStreamBatchingFifoIpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 1 , TID_BITS_C = > 1 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 1 , TUSER_MODE_C = > TUSER_NORMAL_C )

Signals
axiResetN	sl := ' 1 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_s_axis	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_m_axis	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiStreamBatchingFifo <Entity AxiStreamBatchingFifo>

The documentation for this design unit was generated from the following file:

Constants

Signals