AxiLiteSequencerRamIpIntegrator.rtl Architecture Reference

Architecture >> AxiLiteSequencerRamIpIntegrator::rtl

Signals
sAxiAResetN	sl := ' 1 '
sAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
sAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
sAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
sAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
mAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
mAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
mAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
mAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_slaveshimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_mastershimlayer	MasterAxiLiteIpIntegrator <Entity MasterAxiLiteIpIntegrator>
u_dut	AxiLiteSequencerRam <Entity AxiLiteSequencerRam>

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd