AxiLiteSequencerRamIpIntegrator Entity Reference

Inheritance diagram for AxiLiteSequencerRamIpIntegrator:

Collaboration diagram for AxiLiteSequencerRamIpIntegrator:

Entities
AxiLiteSequencerRamIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
WAIT_FOR_RESPONSE_G	boolean := false
READ_LATENCY_G	natural range 0 to 3 := 1
ADDR_WIDTH_G	positive := 4

Ports
axilClk	in	sl
axilRst	in	sl
extStart	in	sl := ' 0 '
extSize	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
extBusy	out	sl
extDone	out	sl
S_AXI_AWADDR	in	slv ( 31 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 31 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
M_AXI_AWADDR	out	slv ( 31 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WDATA	out	slv ( 31 downto 0 )
M_AXI_WSTRB	out	slv ( 3 downto 0 )
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl
M_AXI_ARADDR	out	slv ( 31 downto 0 )
M_AXI_ARPROT	out	slv ( 2 downto 0 )
M_AXI_ARVALID	out	sl
M_AXI_ARREADY	in	sl
M_AXI_RDATA	in	slv ( 31 downto 0 )
M_AXI_RRESP	in	slv ( 1 downto 0 )
M_AXI_RVALID	in	sl
M_AXI_RREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd