AxiLiteSequencerRam Entity Reference

Inheritance diagram for AxiLiteSequencerRam:

Collaboration diagram for AxiLiteSequencerRam:

Entities
AxiLiteSequencerRam.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
MEMORY_INIT_FILE_G	string := " none "
MEMORY_INIT_PARAM_G	string := " 0 "
WAIT_FOR_RESPONSE_G	boolean := false
READ_LATENCY_G	natural range 0 to 3 := 2
ADDR_WIDTH_G	positive := 8

Ports
axilClk	in	sl
axilRst	in	sl
extStart	in	sl := ' 0 '
extSize	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
extBusy	out	sl
extDone	out	sl
sAxilReadMaster	in	AxiLiteReadMasterType
sAxilReadSlave	out	AxiLiteReadSlaveType
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType
mAxilReadMaster	out	AxiLiteReadMasterType
mAxilReadSlave	in	AxiLiteReadSlaveType
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteSequencerRam.vhd
• build/SRC_VHDL/surf/AxiLiteSequencerRam.vhd