AxiLiteSequencerRam.rtl Architecture Reference

Architecture >> AxiLiteSequencerRam::rtl

Processes
comb	( ack , axilRst , dout , extSize , extStart , r , sAxilReadMaster , sAxilWriteMaster , seqData )
seq	( axilClk , axilRst )
comb	( ack , axilRst , dout , extSize , extStart , r , sAxilReadMaster , sAxilWriteMaster , seqData )
seq	( axilClk , axilRst )

Constants
AXI_RAM_ADDR_HIGH_C	integer := ADDR_WIDTH_G+ AXI_DEC_ADDR_RANGE_C ' high
AXI_RAM_ADDR_LOW_C	integer := AXI_DEC_ADDR_RANGE_C ' high+ 1
REG_INIT_C	RegType := ( extBusy = > ' 0 ' , extDone = > ' 0 ' , sAxilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , sAxilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , wstrb = > ( others = > ' 0 ' ) , din = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , size = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) , seqAddr = > ( others = > ' 0 ' ) , resp = > ( others = > ' 0 ' ) , rdLatecy = > 0 , req = > AXI_LITE_REQ_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , S_AXI_RD_S , M_AXI_REQ_S , M_AXI_ACK_S , SEQ_DONE_S )

Subtypes
AXI_DEC_ADDR_RANGE_C	integer range 2 downto 2
AXI_RAM_ADDR_RANGE_C	integer range AXI_RAM_ADDR_HIGH_C downto AXI_RAM_ADDR_LOW_C

Signals
r	RegType := REG_INIT_C
rin	RegType
seqData	slv ( 63 downto 0 )
dout	slv ( 63 downto 0 )
ack	AxiLiteAckType

Records
RegType

Instantiations
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>
u_ram	TrueDualPortRamXpm <Entity TrueDualPortRamXpm>
u_ram	TrueDualPortRamAlteraMf <Entity TrueDualPortRamAlteraMf>
u_ram	TrueDualPortRam <Entity TrueDualPortRam>
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>
u_ram	TrueDualPortRamXpm <Entity TrueDualPortRamXpm>
u_ram	TrueDualPortRamAlteraMf <Entity TrueDualPortRamAlteraMf>
u_ram	TrueDualPortRam <Entity TrueDualPortRam>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteSequencerRam.vhd
• build/SRC_VHDL/surf/AxiLiteSequencerRam.vhd