MasterAxiLiteIpIntegrator Entity Reference

Inheritance diagram for MasterAxiLiteIpIntegrator:

Collaboration diagram for MasterAxiLiteIpIntegrator:

Entities
MasterAxiLiteIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
INTERFACENAME	string := " M_AXI "
EN_ERROR_RESP	boolean := false
HAS_PROT	natural range 0 to 1 := 0
HAS_WSTRB	natural range 0 to 1 := 0
FREQ_HZ	positive := 100000000
ADDR_WIDTH	positive := 12

Ports
M_AXI_ACLK	in	std_logic
M_AXI_ARESETN	in	std_logic
M_AXI_AWADDR	out	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
M_AXI_AWPROT	out	std_logic_vector ( 2 downto 0 )
M_AXI_AWVALID	out	std_logic
M_AXI_AWREADY	in	std_logic
M_AXI_WDATA	out	std_logic_vector ( 31 downto 0 )
M_AXI_WSTRB	out	std_logic_vector ( 3 downto 0 )
M_AXI_WVALID	out	std_logic
M_AXI_WREADY	in	std_logic
M_AXI_BRESP	in	std_logic_vector ( 1 downto 0 )
M_AXI_BVALID	in	std_logic
M_AXI_BREADY	out	std_logic
M_AXI_ARADDR	out	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
M_AXI_ARPROT	out	std_logic_vector ( 2 downto 0 )
M_AXI_ARVALID	out	std_logic
M_AXI_ARREADY	in	std_logic
M_AXI_RDATA	in	std_logic_vector ( 31 downto 0 )
M_AXI_RRESP	in	std_logic_vector ( 1 downto 0 )
M_AXI_RVALID	in	std_logic
M_AXI_RREADY	out	std_logic
axilClk	out	sl
axilRst	out	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd
• build/SRC_VHDL/surf/MasterAxiLiteIpIntegrator.vhd