Architecture >> AxiLiteIpBusBridgeTb::testbed

Constants
GET_BUILD_INFO_C	BuildInfoRetType := toBuildInfo ( BUILD_INFO_C )
MOD_BUILD_INFO_C	BuildInfoRetType := ( buildString = > GET_BUILD_INFO_C.buildString , fwVersion = > GET_BUILD_INFO_C.fwVersion , gitHash = > x " 1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA " )
SIM_BUILD_INFO_C	slv ( 2239 downto 0 ) := toSlv ( MOD_BUILD_INFO_C )
CLK_PERIOD_G	time := 10 ns
TPD_G	time := CLK_PERIOD_G/ 4

Signals
axilClk	sl := ' 0 '
axilRst	sl := ' 0 '
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
ipbRdata	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
ipbAck	sl := ' 0 '
ipbErr	sl := ' 0 '
ipbAddr	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
ipbWdata	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
ipbStrobe	sl := ' 0 '
ipbWrite	sl := ' 0 '
regWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
regWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
regReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
regReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C

Instantiations
u_axilclk	ClkRst <Entity ClkRst>
u_axilitetoipbus	AxiLiteToIpBus <Entity AxiLiteToIpBus>
u_ipbustoaxilite	IpBusToAxiLite <Entity IpBusToAxiLite>
u_version	AxiVersion <Entity AxiVersion>
u_axilclk	ClkRst <Entity ClkRst>
u_axilitetoipbus	AxiLiteToIpBus <Entity AxiLiteToIpBus>
u_ipbustoaxilite	IpBusToAxiLite <Entity IpBusToAxiLite>
u_version	AxiVersion <Entity AxiVersion>

The documentation for this design unit was generated from the following files:

Processes

Constants