IpBusToAxiLite Entity Reference

Inheritance diagram for IpBusToAxiLite:

Collaboration diagram for IpBusToAxiLite:

Entities
IpBusToAxiLite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns

Ports
clk	in	sl
rst	in	sl
ipbAddr	in	slv ( 31 downto 0 )
ipbWdata	in	slv ( 31 downto 0 )
ipbStrobe	in	sl
ipbWrite	in	sl
ipbRdata	out	slv ( 31 downto 0 )
ipbAck	out	sl
ipbErr	out	sl
axilReadMaster	out	AxiLiteReadMasterType
axilReadSlave	in	AxiLiteReadSlaveType
axilWriteMaster	out	AxiLiteWriteMasterType
axilWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/IpBusToAxiLite.vhd
• build/SRC_VHDL/surf/IpBusToAxiLite.vhd