IpBusToAxiLite.rtl Architecture Reference

Architecture >> IpBusToAxiLite::rtl

Processes
comb	( ack , ipbAddr , ipbStrobe , ipbWdata , ipbWrite , r , rst )
seq	( clk , rst )
comb	( ack , ipbAddr , ipbStrobe , ipbWdata , ipbWrite , r , rst )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( ipbRdata = > ( others = > ' 0 ' ) , ipbAck = > ' 0 ' , ipbErr = > ' 0 ' , req = > AXI_LITE_REQ_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , WAIT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
ack	AxiLiteAckType

Records
RegType

Instantiations
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/IpBusToAxiLite.vhd
• build/SRC_VHDL/surf/IpBusToAxiLite.vhd