AxiLiteCrossbarTerminationIpIntegrator.mapping Architecture Reference

Architecture >> AxiLiteCrossbarTerminationIpIntegrator::mapping

Constants
NUM_AXIL_MASTERS_C	positive := 5
AXIL_XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , x " 0000_0000 " , 16 , 12 )
NUM_CASCADE_MASTERS_C	positive := 2
CASCADE_XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_CASCADE_MASTERS_C , x " 0000_4000 " , 12 , 11 )

Signals
axilClk	sl
axilRst	sl
axilReadMasters	AxiLiteReadMasterArray ( 1 downto 0 )
axilReadSlaves	AxiLiteReadSlaveArray ( 1 downto 0 )
axilWriteMasters	AxiLiteWriteMasterArray ( 1 downto 0 )
axilWriteSlaves	AxiLiteWriteSlaveArray ( 1 downto 0 )
xbarReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
xbarReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( 1 = > AXI_LITE_READ_SLAVE_EMPTY_OK_C , 2 = > AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C , 3 = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C , others = > AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C )
xbarWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
xbarWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( 1 = > AXI_LITE_WRITE_SLAVE_EMPTY_OK_C , 2 = > AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C , 3 = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C , others = > AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C )
cascadeReadMasters	AxiLiteReadMasterArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 )
cascadeReadSlaves	AxiLiteReadSlaveArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C )
cascadeWriteMasters	AxiLiteWriteMasterArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 )
cascadeWriteSlaves	AxiLiteWriteSlaveArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C )

Instantiations
u_shimlayer0	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_shimlayer1	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axil_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>
u_cascade_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_cascade_mem	AxiDualPortRam <Entity AxiDualPortRam>

---

The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteCrossbarTerminationIpIntegrator.vhd