AxiLiteCrossbarTerminationIpIntegrator Entity Reference

Inheritance diagram for AxiLiteCrossbarTerminationIpIntegrator:

Collaboration diagram for AxiLiteCrossbarTerminationIpIntegrator:

Entities
AxiLiteCrossbarTerminationIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Ports
S_AXI_ACLK	in	std_logic
S_AXI_ARESETN	in	std_logic
S0_AXI_AWADDR	in	std_logic_vector ( 31 downto 0 )
S0_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S0_AXI_AWVALID	in	std_logic
S0_AXI_AWREADY	out	std_logic
S0_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S0_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S0_AXI_WVALID	in	std_logic
S0_AXI_WREADY	out	std_logic
S0_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S0_AXI_BVALID	out	std_logic
S0_AXI_BREADY	in	std_logic
S0_AXI_ARADDR	in	std_logic_vector ( 31 downto 0 )
S0_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S0_AXI_ARVALID	in	std_logic
S0_AXI_ARREADY	out	std_logic
S0_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S0_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S0_AXI_RVALID	out	std_logic
S0_AXI_RREADY	in	std_logic
S1_AXI_AWADDR	in	std_logic_vector ( 31 downto 0 )
S1_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S1_AXI_AWVALID	in	std_logic
S1_AXI_AWREADY	out	std_logic
S1_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S1_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S1_AXI_WVALID	in	std_logic
S1_AXI_WREADY	out	std_logic
S1_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S1_AXI_BVALID	out	std_logic
S1_AXI_BREADY	in	std_logic
S1_AXI_ARADDR	in	std_logic_vector ( 31 downto 0 )
S1_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S1_AXI_ARVALID	in	std_logic
S1_AXI_ARREADY	out	std_logic
S1_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S1_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S1_AXI_RVALID	out	std_logic
S1_AXI_RREADY	in	std_logic

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteCrossbarTerminationIpIntegrator.vhd