Architecture >> AxiLiteCrossbarTb::mapping

Constants
NUM_AXIL_MASTERS_C	positive := 2
AXIL_XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , x " 0000_0000 " , 22 , 20 )
NUM_CASCADE_MASTERS_C	positive := 2
CASCADE_XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 ) := ( 0 = > ( baseAddr = > x " 0010_2000 " , addrBits = > 12 , connectivity = > X " 0001 " ) , 1 = > ( baseAddr = > x " 0016_0000 " , addrBits = > 17 , connectivity = > X " 0001 " ) )

Signals
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )
cascadeReadMasters	AxiLiteReadMasterArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 )
cascadeReadSlaves	AxiLiteReadSlaveArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
cascadeWriteMasters	AxiLiteWriteMasterArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 )
cascadeWriteSlaves	AxiLiteWriteSlaveArray ( NUM_CASCADE_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axil_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>
u_cascade_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axil_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>
u_cascade_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>

The documentation for this design unit was generated from the following files:

Constants

Signals