AxiLiteAsyncTb.tb Architecture Reference

Architecture >> AxiLiteAsyncTb::tb

Processes
test
test

Constants
TPD_G	time := 1 ns
NUM_ADDR_BITS_G	natural := 32
PIPE_STAGES_G	integer range 0 to 16 := 0

Signals
sAxiClk	sl
sAxiClkRst	sl
sAxiReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
sAxiReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
sAxiWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
sAxiWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
mAxiClk	sl
mAxiClkRst	sl
mAxiReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
mAxiReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
mAxiWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
mAxiWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
intAxiReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
intAxiReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
intAxiWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
intAxiWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_axilitecrossbar_1	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>
u_clkrst_1	ClkRst <Entity ClkRst>
u_clkrst_2	ClkRst <Entity ClkRst>
u_axilitecrossbar_1	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>
u_clkrst_1	ClkRst <Entity ClkRst>
u_clkrst_2	ClkRst <Entity ClkRst>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/tb/AxiLiteAsyncTb.vhd
• build/SRC_VHDL/surf/AxiLiteAsyncTb.vhd