AdcDdrPhy7Series.rtl Architecture Reference

Architecture >> AdcDdrPhy7Series::rtl

Functions
string	bufrDivide ( value: in positive )

Signals
dClkPad	sl
bitClk	sl
bitClkInv	sl
wordClk	sl
wordRst	sl
deserReset	sl
fcoPad	slv ( FCO_LANES_G- 1 downto 0 )
dataPad	slv ( DATA_LANES_G- 1 downto 0 )

Instantiations
u_delayreadysync	Synchronizer <Entity Synchronizer>
u_dcoinput	ibufds
u_bitclock	bufio
u_wordclock	bufr
u_wordreset	RstSync <Entity RstSync>
u_input	ibufds
u_deserializer	AdcDdrDeserializer7Series <Entity AdcDdrDeserializer7Series>
u_input	ibufds
u_deserializer	AdcDdrDeserializer7Series <Entity AdcDdrDeserializer7Series>

---

The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/7Series/rtl/AdcDdrPhy7Series.vhd