AdcDdrDeserializer7Series Entity Reference

Inheritance diagram for AdcDdrDeserializer7Series:

Entities
AdcDdrDeserializer7Series.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
IODELAY_GROUP_G	string := " DEFAULT_GROUP "
IDELAYCTRL_FREQ_G	real := 200 . 0
SERIALIZATION_FACTOR_G	positive := 14

Ports
bitClk	in	sl
bitClkInv	in	sl
wordClk	in	sl
rst	in	sl
bitSlip	in	sl
delayClk	in	sl
delayValue	in	slv ( 4 downto 0 )
delayLoad	in	sl
serialData	in	sl
dataWord	out	slv ( SERIALIZATION_FACTOR_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/7Series/rtl/AdcDdrDeserializer7Series.vhd