AdcDdrPhy7Series Entity Reference

Inheritance diagram for AdcDdrPhy7Series:

Collaboration diagram for AdcDdrPhy7Series:

Entities
AdcDdrPhy7Series.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AdcDdrPkg	Package <AdcDdrPkg>
vcomponents

Generics
TPD_G	time := 1 ns
DATA_LANES_G	positive := 8
FCO_LANES_G	positive := 1
SERIALIZATION_FACTOR_G	positive := 14
IODELAY_GROUP_G	string := " DEFAULT_GROUP "
IDELAYCTRL_FREQ_G	real := 200 . 0
DATA_FCO_MAP_G	NaturalArray ( DATA_LANES_G- 1 downto 0 ) := ( others = > 0 )

Ports
adcClkRst	in	sl
idelayCtrlRdy	in	sl := ' 0 '
phyReset	in	sl
dClkP	in	sl
dClkN	in	sl
fcoP	in	slv ( FCO_LANES_G- 1 downto 0 )
fcoN	in	slv ( FCO_LANES_G- 1 downto 0 )
dataP	in	slv ( DATA_LANES_G- 1 downto 0 )
dataN	in	slv ( DATA_LANES_G- 1 downto 0 )
bitSlip	in	slv ( FCO_LANES_G- 1 downto 0 )
dataDelayWrite	in	AdcDdrDelayArray ( DATA_LANES_G- 1 downto 0 )
fcoDelayWrite	in	AdcDdrDelayArray ( FCO_LANES_G- 1 downto 0 )
captureClk	out	sl
captureRst	out	sl
delayReady	out	sl
dataWord	out	Slv16Array ( DATA_LANES_G- 1 downto 0 )
dataValid	out	slv ( DATA_LANES_G- 1 downto 0 )
fcoWord	out	Slv16Array ( FCO_LANES_G- 1 downto 0 )
fcoValid	out	slv ( FCO_LANES_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/7Series/rtl/AdcDdrPhy7Series.vhd