- Generated by
1.9.8
|
SURF
|
Functions | |
| Slv9Array | delayValuesToSlv ( values: in NaturalArray , delayClass: in string ) |
Processes | |
| comb | ( captureRst , delayReady , fcoValid , fcoWord , fifoOverflow , r , sampleIn , sampleValid , xbarMasterReadMasters , xbarMasterWriteMasters ) |
| seq | ( captureClk ) |
| format | ( fifoOut , fifoValid ) |
Constants | |
| FIFO_WIDTH_C | positive := ( 16 * CHANNELS_G ) + 1 |
| AXIS_CONFIG_C | AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 2 , TDEST_BITS_C = > 8 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_FIXED_C , TUSER_BITS_C = > 1 , TUSER_MODE_C = > TUSER_NORMAL_C ) |
| AXIL_CONFIG_C | AxiLiteCrossbarMasterConfigArray ( 1 downto 0 ) := ( 0 = > ( baseAddr = > AXIL_BASE_ADDR_G , addrBits = > 11 , connectivity = > x " 0001 " ) , 1 = > ( baseAddr = > AXIL_BASE_ADDR_G+ resize ( ADC_DDR_PATTERN_BASE_ADDR_C , 32 ) , addrBits = > 8 , connectivity = > x " 0001 " ) ) |
| REG_INIT_C | RegType := ( phyReset = > ' 0 ' , startupPending = > ' 1 ' , resetHold = > ADC_DDR_RESET_HOLD_C , relock = > ' 0 ' , clearCounters = > ' 0 ' , bitSlip = > ( others = > ' 0 ' ) , locked = > ( others = > ' 0 ' ) , matchCount = > ( others = > 0 ) , errorCount = > ( others = > 0 ) , slipWait = > ( others = > 0 ) , lostLockCount = > ( others = > ( others = > ' 0 ' ) ) , overflowCount = > ( others = > ' 0 ' ) , overflow = > ' 0 ' , dataDelay = > delayValuesToSlv ( DATA_DELAY_INIT_G , " data " ) , fcoDelay = > delayValuesToSlv ( FCO_DELAY_INIT_G , " FCO " ) , dataDelayLoad = > ( others = > ' 0 ' ) , fcoDelayLoad = > ( others = > ' 0 ' ) , debugBusy = > ' 0 ' , debugIndex = > 0 , snapshotSeq = > ( others = > ' 0 ' ) , debugWorking = > ( others = > ( others = > ' 0 ' ) ) , debugSample = > ( others = > ( others = > ' 0 ' ) ) , formatted = > ( others = > ( others = > ' 0 ' ) ) , sampleValid = > ' 0 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C ) |
Types | |
| FcoCountArray | array ( natural range <> ) of natural range 0 to ADC_DDR_LOCK_MATCHES_C |
| FcoErrorArray | array ( natural range <> ) of natural range 0 to ADC_DDR_UNLOCK_ERRORS_C |
| FcoWaitArray | array ( natural range <> ) of natural range 0 to ADC_DDR_BITSLIP_INTERVAL_C- 1 |
Signals | |
| r | RegType := REG_INIT_C |
| rin | RegType |
| syncAxilReadMaster | AxiLiteReadMasterType |
| syncAxilReadSlave | AxiLiteReadSlaveType |
| syncAxilWriteMaster | AxiLiteWriteMasterType |
| syncAxilWriteSlave | AxiLiteWriteSlaveType |
| xbarMasterReadMasters | AxiLiteReadMasterArray ( 1 downto 0 ) |
| xbarMasterReadSlaves | AxiLiteReadSlaveArray ( 1 downto 0 ) |
| xbarMasterWriteMasters | AxiLiteWriteMasterArray ( 1 downto 0 ) |
| xbarMasterWriteSlaves | AxiLiteWriteSlaveArray ( 1 downto 0 ) |
| fifoIn | slv ( FIFO_WIDTH_C- 1 downto 0 ) |
| fifoOut | slv ( FIFO_WIDTH_C- 1 downto 0 ) |
| fifoValid | sl |
| fifoOverflow | sl |
Records | |
| RegType | |
Instantiations | |
| u_axiliteasync | AxiLiteAsync <Entity AxiLiteAsync> |
| u_axilitecrossbar | AxiLiteCrossbar <Entity AxiLiteCrossbar> |
| u_patterntester | AdcDdrPatternTester <Entity AdcDdrPatternTester> |
| u_datafifo | FifoAsync <Entity FifoAsync> |
1.9.8