AdcDdrPatternTester Entity Reference

Inheritance diagram for AdcDdrPatternTester:

Entities
AdcDdrPatternTester.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AdcDdrPkg	Package <AdcDdrPkg>

Generics
TPD_G	time := 1 ns
CHANNELS_G	positive := 8
FCO_LANES_G	positive := 1
SAMPLE_WIDTH_G	positive range 2 to 16 := 14
SERIALIZATION_FACTOR_G	positive := 14
FRAME_PATTERN_G	slv := " 11111110000000 "

Ports
clk	in	sl
rst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
sampleValid	in	sl
sampleIn	in	Slv16Array ( CHANNELS_G- 1 downto 0 )
fcoValid	in	slv ( FCO_LANES_G- 1 downto 0 )
fcoWord	in	Slv16Array ( FCO_LANES_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/rtl/AdcDdrPatternTester.vhd