AdcDdrCore Entity Reference

Inheritance diagram for AdcDdrCore:

Collaboration diagram for AdcDdrCore:

Entities
AdcDdrCore.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
AdcDdrPkg	Package <AdcDdrPkg>

Generics
TPD_G	time := 1 ns
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
DATA_LANES_G	positive := 8
FCO_LANES_G	positive := 1
CHANNELS_G	positive := 8
SAMPLE_WIDTH_G	positive range 2 to 16 := 14
SERIALIZATION_FACTOR_G	positive := 14
DELAY_BITS_G	positive range 1 to 9 := 5
DATA_DELAY_INIT_G	NaturalArray ( DATA_LANES_G- 1 downto 0 ) := ( others = > 0 )
FCO_DELAY_INIT_G	NaturalArray ( FCO_LANES_G- 1 downto 0 ) := ( others = > 0 )
FIFO_ADDR_WIDTH_G	positive := 4
FRAME_PATTERN_G	slv := " 11111110000000 "
PATTERN_CHECK_G	boolean := true
OFFSET_BINARY_G	boolean := false
NEGATE_G	boolean := false

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
captureClk	in	sl
captureRst	in	sl
delayReady	in	sl
fcoWord	in	Slv16Array ( FCO_LANES_G- 1 downto 0 )
fcoValid	in	slv ( FCO_LANES_G- 1 downto 0 ) := ( others = > ' 1 ' )
sampleValid	in	sl
sampleIn	in	Slv16Array ( CHANNELS_G- 1 downto 0 )
phyReset	out	sl
bitSlip	out	slv ( FCO_LANES_G- 1 downto 0 )
dataDelayWrite	out	AdcDdrDelayArray ( DATA_LANES_G- 1 downto 0 )
fcoDelayWrite	out	AdcDdrDelayArray ( FCO_LANES_G- 1 downto 0 )
streamClk	in	sl
streamRst	in	sl
streams	out	AxiStreamMasterArray ( CHANNELS_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/rtl/AdcDdrCore.vhd