SURF  1.0
TenGigEthGthUltraScaleClk.vhd
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1 -------------------------------------------------------------------------------
2 -- File : TenGigEthGthUltraScaleClk.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-04-08
5 -- Last update: 2016-04-19
6 -------------------------------------------------------------------------------
7 -- Description: 10GBASE-R Ethernet's Clock Module
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 
23 library unisim;
24 use unisim.vcomponents.all;
25 
26 --! @see entity
27  --! @ingroup ethernet_TenGigEthCore_gthUltraScale
28 entity TenGigEthGthUltraScaleClk is
29  generic (
30  TPD_G : time := 1 ns;
31  REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz
32  QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001");
33  port (
34  -- MGT Clock Port (156.25 MHz or 312.5 MHz)
35  gtRefClk : in sl := '0';
36  gtClkP : in sl := '1';
37  gtClkN : in sl := '0';
38  coreClk : out sl;
39  coreRst : in sl := '0';
40  gtClk : out sl;
41  -- Quad PLL Ports
42  qplllock : out sl;
43  qplloutclk : out sl;
44  qplloutrefclk : out sl;
45  qpllRst : in sl);
46 end TenGigEthGthUltraScaleClk;
47 
48 architecture mapping of TenGigEthGthUltraScaleClk is
49 
50  constant DIV_C : slv(2 downto 0) := ite((REF_CLK_FREQ_G = 156.25E+6), "000", "001");
51 
52  signal refClk : sl;
53  signal refClkCopy : sl;
54  signal refClock : sl;
55  signal coreClock : sl;
56  signal qpllReset : sl;
57 
58 begin
59 
60  gtClk <= refClock;
61 
62  IBUFDS_GTE3_Inst : IBUFDS_GTE3
63  generic map (
64  REFCLK_EN_TX_PATH => '0',
65  REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O
66  REFCLK_ICNTL_RX => "00")
67  port map (
68  I => gtClkP,
69  IB => gtClkN,
70  CEB => '0',
71  ODIV2 => refClkCopy,
72  O => refClk);
73 
74  BUFG_GT_Inst : BUFG_GT
75  port map (
76  I => refClkCopy,
77  CE => '1',
78  CEMASK => '1',
79  CLR => '0',
80  CLRMASK => '1',
81  DIV => DIV_C,
82  O => coreClock);
83 
84  refClock <= gtRefClk when(QPLL_REFCLK_SEL_G = "111") else refClk;
85  coreClk <= gtRefClk when(QPLL_REFCLK_SEL_G = "111") else coreClock;
86  qpllReset <= qpllRst or coreRst;
87 
88  GEN_156p25MHz : if (REF_CLK_FREQ_G = 156.25E+6) generate
89  GthUltraScaleQuadPll_Inst : entity work.GthUltraScaleQuadPll
90  generic map (
91  -- Simulation Parameters
92  TPD_G => TPD_G,
93  SIM_RESET_SPEEDUP_G => "FALSE",
94  SIM_VERSION_G => 2,
95  -- QPLL Configuration Parameters
96  QPLL_CFG0_G => (others => x"301C"),
97  QPLL_CFG1_G => (others => x"0018"),
98  QPLL_CFG1_G3_G => (others => x"0018"),
99  QPLL_CFG2_G => (others => x"0048"),
100  QPLL_CFG2_G3_G => (others => x"0048"),
101  QPLL_CFG3_G => (others => x"0120"),
102  QPLL_CFG4_G => (others => x"0009"),
103  QPLL_CP_G => (others => "0000011111"),
104  QPLL_CP_G3_G => (others => "1111111111"),
105  QPLL_FBDIV_G => (others => 66),
106  QPLL_FBDIV_G3_G => (others => 80),
107  QPLL_INIT_CFG0_G => (others => x"0000"),
108  QPLL_INIT_CFG1_G => (others => x"00"),
109  QPLL_LOCK_CFG_G => (others => x"25E8"),
110  QPLL_LOCK_CFG_G3_G => (others => x"25E8"),
111  QPLL_LPF_G => (others => "1111111111"),
112  QPLL_LPF_G3_G => (others => "0000010101"),
113  QPLL_REFCLK_DIV_G => (others => 1),
114  QPLL_SDM_CFG0_G => (others => x"0000"),
115  QPLL_SDM_CFG1_G => (others => x"0000"),
116  QPLL_SDM_CFG2_G => (others => x"0000"),
117  -- Clock Selects
118  QPLL_REFCLK_SEL_G => (others => QPLL_REFCLK_SEL_G))
119  port map (
120  qPllRefClk(0) => refClock,
121  qPllRefClk(1) => '0',
122  qPllOutClk(0) => qPllOutClk,
123  qPllOutClk(1) => open,
124  qPllOutRefClk(0) => qPllOutRefClk,
125  qPllOutRefClk(1) => open,
126  qPllLock(0) => qPllLock,
127  qPllLock(1) => open,
128  qPllLockDetClk(0) => '0', -- IP Core ties this to GND (see note below)
129  qPllLockDetClk(1) => '0', -- IP Core ties this to GND (see note below)
130  qPllPowerDown(0) => '0',
131  qPllPowerDown(1) => '1',
132  qPllReset(0) => qpllReset,
133  qPllReset(1) => '1');
134  end generate;
135  GEN_312p5MHz : if (REF_CLK_FREQ_G = 312.50E+6) generate
136  GthUltraScaleQuadPll_Inst : entity work.GthUltraScaleQuadPll
137  generic map (
138  -- Simulation Parameters
139  TPD_G => TPD_G,
140  SIM_RESET_SPEEDUP_G => "FALSE",
141  SIM_VERSION_G => 2,
142  -- QPLL Configuration Parameters
143  QPLL_CFG0_G => (others => x"301C"),
144  QPLL_CFG1_G => (others => x"0018"),
145  QPLL_CFG1_G3_G => (others => x"0018"),
146  QPLL_CFG2_G => (others => x"0048"),
147  QPLL_CFG2_G3_G => (others => x"0048"),
148  QPLL_CFG3_G => (others => x"0120"),
149  QPLL_CFG4_G => (others => x"0009"),
150  QPLL_CP_G => (others => "0000011111"),
151  QPLL_CP_G3_G => (others => "1111111111"),
152  QPLL_FBDIV_G => (others => 66),
153  QPLL_FBDIV_G3_G => (others => 80),
154  QPLL_INIT_CFG0_G => (others => x"0000"),
155  QPLL_INIT_CFG1_G => (others => x"00"),
156  QPLL_LOCK_CFG_G => (others => x"25E8"),
157  QPLL_LOCK_CFG_G3_G => (others => x"25E8"),
158  QPLL_LPF_G => (others => "1111111111"),
159  QPLL_LPF_G3_G => (others => "0000010101"),
160  QPLL_REFCLK_DIV_G => (others => 2),
161  QPLL_SDM_CFG0_G => (others => x"0000"),
162  QPLL_SDM_CFG1_G => (others => x"0000"),
163  QPLL_SDM_CFG2_G => (others => x"0000"),
164  -- Clock Selects
165  QPLL_REFCLK_SEL_G => (others => QPLL_REFCLK_SEL_G))
166  port map (
167  qPllRefClk(0) => refClock,
168  qPllRefClk(1) => '0',
169  qPllOutClk(0) => qPllOutClk,
170  qPllOutClk(1) => open,
171  qPllOutRefClk(0) => qPllOutRefClk,
172  qPllOutRefClk(1) => open,
173  qPllLock(0) => qPllLock,
174  qPllLock(1) => open,
175  qPllLockDetClk(0) => '0', -- IP Core ties this to GND (see note below)
176  qPllLockDetClk(1) => '0', -- IP Core ties this to GND (see note below)
177  qPllPowerDown(0) => '0',
178  qPllPowerDown(1) => '1',
179  qPllReset(0) => qpllReset,
180  qPllReset(1) => '1');
181  end generate;
182  ---------------------------------------------------------------------------------------------
183  -- Note: GTXE3_COMMON pin GTHE3_COMMON_Inst.QPLLLOCKDETCLK[1:0] cannot be driven by a clock
184  -- derived from the same clock used as the reference clock for the QPLL, including
185  -- TXOUTCLK*, RXOUTCLK*, the output from the IBUFDS_GTE2 providing the reference clock,
186  -- and any -- buffered or multiplied/divided versions of these clock outputs.
187  -- Please see UG576 for more information. Source, through a clock buffer, is the same
188  -- as the GT cell reference clock.
189  ---------------------------------------------------------------------------------------------
190 
191 end mapping;
GthUltraScaleQuadPll.QPLL_LPF_G3_G
QPLL_LPF_G3_GSlv10Array( 1 downto 0) :=( others => "1111111111")
Definition: GthUltraScaleQuadPll.vhd:63
GthUltraScaleQuadPll.QPLL_CFG2_G
QPLL_CFG2_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:50
GthUltraScaleQuadPll.QPLL_CFG1_G
QPLL_CFG1_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:48
GthUltraScaleQuadPll.QPLL_CFG2_G3_G
QPLL_CFG2_G3_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:51
GthUltraScaleQuadPll.QPLL_SDM_CFG2_G
QPLL_SDM_CFG2_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:67
GthUltraScaleQuadPll.QPLL_SDM_CFG1_G
QPLL_SDM_CFG1_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:66
TenGigEthGthUltraScaleClk.QPLL_REFCLK_SEL_G
QPLL_REFCLK_SEL_Gslv( 2 downto 0) := "001"
Definition: TenGigEthGthUltraScaleClk.vhd:32
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
GthUltraScaleQuadPll.SIM_RESET_SPEEDUP_G
SIM_RESET_SPEEDUP_Gstring := "FALSE"
Definition: GthUltraScaleQuadPll.vhd:33
GthUltraScaleQuadPll.QPLL_LPF_G
QPLL_LPF_GSlv10Array( 1 downto 0) :=( others => "1111111111")
Definition: GthUltraScaleQuadPll.vhd:62
GthUltraScaleQuadPll.QPLL_LOCK_CFG_G
QPLL_LOCK_CFG_GSlv16Array( 1 downto 0) :=( others => x"01E8")
Definition: GthUltraScaleQuadPll.vhd:60
GthUltraScaleQuadPll.QPLL_CFG4_G
QPLL_CFG4_GSlv16Array( 1 downto 0) :=( others => x"0009")
Definition: GthUltraScaleQuadPll.vhd:53
TenGigEthGthUltraScaleClk.mapping.DIV_C
slv( 2 downto 0) := ite(( REF_CLK_FREQ_G= 156.25E+6), "000", "001") DIV_C
Definition: TenGigEthGthUltraScaleClk.vhd:50
GthUltraScaleQuadPll.QPLL_INIT_CFG1_G
QPLL_INIT_CFG1_GSlv8Array( 1 downto 0) :=( others => x"00")
Definition: GthUltraScaleQuadPll.vhd:59
GthUltraScaleQuadPll.QPLL_CFG0_G
QPLL_CFG0_GSlv16Array( 1 downto 0) :=( others => x"3018")
Definition: GthUltraScaleQuadPll.vhd:47
GthUltraScaleQuadPll.QPLL_CFG1_G3_G
QPLL_CFG1_G3_GSlv16Array( 1 downto 0) :=( others => x"0020")
Definition: GthUltraScaleQuadPll.vhd:49
GthUltraScaleQuadPll.QPLL_LOCK_CFG_G3_G
QPLL_LOCK_CFG_G3_GSlv16Array( 1 downto 0) :=( others => x"01E8")
Definition: GthUltraScaleQuadPll.vhd:61
GthUltraScaleQuadPll.QPLL_FBDIV_G
QPLL_FBDIV_GNaturalArray( 1 downto 0) :=( others => 66)
Definition: GthUltraScaleQuadPll.vhd:56
GthUltraScaleQuadPll.QPLL_CP_G
QPLL_CP_GSlv10Array( 1 downto 0) :=( others => "0000011111")
Definition: GthUltraScaleQuadPll.vhd:54
GthUltraScaleQuadPll.QPLL_CP_G3_G
QPLL_CP_G3_GSlv10Array( 1 downto 0) :=( others => "0000011111")
Definition: GthUltraScaleQuadPll.vhd:55
GthUltraScaleQuadPll.QPLL_CFG3_G
QPLL_CFG3_GSlv16Array( 1 downto 0) :=( others => x"0120")
Definition: GthUltraScaleQuadPll.vhd:52
GthUltraScaleQuadPll.QPLL_FBDIV_G3_G
QPLL_FBDIV_G3_GNaturalArray( 1 downto 0) :=( others => 80)
Definition: GthUltraScaleQuadPll.vhd:57
GthUltraScaleQuadPll.QPLL_SDM_CFG0_G
QPLL_SDM_CFG0_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:65
GthUltraScaleQuadPll.QPLL_REFCLK_SEL_G
QPLL_REFCLK_SEL_GSlv3Array( 1 downto 0) :=( others => "001")
Definition: GthUltraScaleQuadPll.vhd:69
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
GthUltraScaleQuadPll.QPLL_INIT_CFG0_G
QPLL_INIT_CFG0_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:58
GthUltraScaleQuadPll.QPLL_REFCLK_DIV_G
QPLL_REFCLK_DIV_GNaturalArray( 1 downto 0) :=( others => 2)
Definition: GthUltraScaleQuadPll.vhd:64