SURF  1.0
GthUltraScaleQuadPll.vhd
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1 -------------------------------------------------------------------------------
2 -- File : GthUltraScaleQuadPll.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-04-08
5 -- Last update: 2016-03-08
6 -------------------------------------------------------------------------------
7 -- Description: Wrapper for Ultrascale GTH QPLL primitive
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC MGT Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC MGT Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 use work.AxiLitePkg.all;
23 
24 library unisim;
25 use unisim.vcomponents.all;
26 
27 --! @see entity
28  --! @ingroup xilinx_UltraScale_gthUs
29 entity GthUltraScaleQuadPll is
30  generic (
31  -- Simulation Parameters
32  TPD_G : time := 1 ns;
33  SIM_RESET_SPEEDUP_G : string := "FALSE";
34  SIM_VERSION_G : natural := 2;
35  -- AXI-Lite Parameters
36  AXI_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_DECERR_C;
37  -- QPLL Configuration Parameters
38  BIAS_CFG0_G : slv(15 downto 0) := x"0000";
39  BIAS_CFG1_G : slv(15 downto 0) := x"0000";
40  BIAS_CFG2_G : slv(15 downto 0) := x"0000";
41  BIAS_CFG3_G : slv(15 downto 0) := x"0040";
42  BIAS_CFG4_G : slv(15 downto 0) := x"0000";
43  BIAS_CFG_RSVD_G : slv(9 downto 0) := "0000000000";
44  COMMON_CFG0_G : slv(15 downto 0) := x"0000";
45  COMMON_CFG1_G : slv(15 downto 0) := x"0000";
46  POR_CFG_G : slv(15 downto 0) := x"0004";
47  QPLL_CFG0_G : Slv16Array(1 downto 0) := (others => x"3018");
48  QPLL_CFG1_G : Slv16Array(1 downto 0) := (others => x"0000");
49  QPLL_CFG1_G3_G : Slv16Array(1 downto 0) := (others => x"0020");
50  QPLL_CFG2_G : Slv16Array(1 downto 0) := (others => x"0000");
51  QPLL_CFG2_G3_G : Slv16Array(1 downto 0) := (others => x"0000");
52  QPLL_CFG3_G : Slv16Array(1 downto 0) := (others => x"0120");
53  QPLL_CFG4_G : Slv16Array(1 downto 0) := (others => x"0009");
54  QPLL_CP_G : Slv10Array(1 downto 0) := (others => "0000011111");
55  QPLL_CP_G3_G : Slv10Array(1 downto 0) := (others => "0000011111");
56  QPLL_FBDIV_G : NaturalArray(1 downto 0) := (others => 66);
57  QPLL_FBDIV_G3_G : NaturalArray(1 downto 0) := (others => 80);
58  QPLL_INIT_CFG0_G : Slv16Array(1 downto 0) := (others => x"0000");
59  QPLL_INIT_CFG1_G : Slv8Array(1 downto 0) := (others => x"00");
60  QPLL_LOCK_CFG_G : Slv16Array(1 downto 0) := (others => x"01E8");
61  QPLL_LOCK_CFG_G3_G : Slv16Array(1 downto 0) := (others => x"01E8");
62  QPLL_LPF_G : Slv10Array(1 downto 0) := (others => "1111111111");
63  QPLL_LPF_G3_G : Slv10Array(1 downto 0) := (others => "1111111111");
64  QPLL_REFCLK_DIV_G : NaturalArray(1 downto 0) := (others => 2);
65  QPLL_SDM_CFG0_G : Slv16Array(1 downto 0) := (others => x"0000");
66  QPLL_SDM_CFG1_G : Slv16Array(1 downto 0) := (others => x"0000");
67  QPLL_SDM_CFG2_G : Slv16Array(1 downto 0) := (others => x"0000");
68  -- Clock Selects
69  QPLL_REFCLK_SEL_G : Slv3Array(1 downto 0) := (others => "001"));
70  port (
71  qPllRefClk : in slv(1 downto 0);
72  qPllOutClk : out slv(1 downto 0);
73  qPllOutRefClk : out slv(1 downto 0);
74  qPllFbClkLost : out slv(1 downto 0);
75  qPllLock : out slv(1 downto 0);
76  qPllLockDetClk : in slv(1 downto 0);
77  qPllRefClkLost : out slv(1 downto 0);
78  qPllPowerDown : in slv(1 downto 0) := "00";
79  qPllReset : in slv(1 downto 0);
80  -- AXI-Lite Interface
81  axilClk : in sl := '0';
82  axilRst : in sl := '0';
83  axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
84  axilReadSlave : out AxiLiteReadSlaveType;
85  axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
86  axilWriteSlave : out AxiLiteWriteSlaveType);
87 end entity GthUltraScaleQuadPll;
88 
89 architecture mapping of GthUltraScaleQuadPll is
90 
91  signal gtRefClk0 : slv(1 downto 0);
92  signal gtRefClk1 : slv(1 downto 0);
93  signal gtNorthRefClk0 : slv(1 downto 0);
94  signal gtNorthRefClk1 : slv(1 downto 0);
95  signal gtSouthRefClk0 : slv(1 downto 0);
96  signal gtSouthRefClk1 : slv(1 downto 0);
97  signal gtGRefClk : slv(1 downto 0);
98 
99  signal drpEn : sl;
100  signal drpWe : sl;
101  signal drpRdy : sl;
102  signal drpAddr : slv(8 downto 0);
103  signal drpDi : slv(15 downto 0);
104  signal drpDo : slv(15 downto 0);
105 
106 begin
107 
108  ---------------------------------------------------------------------------------------
109  -- QPLL clock select. Only ever use 1 clock to drive QPLL Channel. Never switch clocks.
110  ---------------------------------------------------------------------------------------
111  GEN_CLK_SELECT :
112  for i in 1 downto 0 generate
113  gtRefClk0(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "001" else '0';
114  gtRefClk1(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "010" else '0';
115  gtNorthRefClk0(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "011" else '0';
116  gtNorthRefClk1(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "100" else '0';
117  gtSouthRefClk0(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "101" else '0';
118  gtSouthRefClk1(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "110" else '0';
119  gtGRefClk(i) <= qpllRefClk(i) when QPLL_REFCLK_SEL_G(i) = "111" else '0';
120  end generate GEN_CLK_SELECT;
121 
122  GTHE3_COMMON_Inst : GTHE3_COMMON
123  generic map (
124  BIAS_CFG0 => BIAS_CFG0_G,
125  BIAS_CFG1 => BIAS_CFG1_G,
126  BIAS_CFG2 => BIAS_CFG2_G,
127  BIAS_CFG3 => BIAS_CFG3_G,
128  BIAS_CFG4 => BIAS_CFG4_G,
129  BIAS_CFG_RSVD => BIAS_CFG_RSVD_G,
130  COMMON_CFG0 => COMMON_CFG0_G,
131  COMMON_CFG1 => COMMON_CFG1_G,
132  POR_CFG => POR_CFG_G,
133  QPLL0_CFG0 => QPLL_CFG0_G(0),
134  QPLL0_CFG1 => QPLL_CFG1_G(0),
135  QPLL0_CFG1_G3 => QPLL_CFG1_G3_G(0),
136  QPLL0_CFG2 => QPLL_CFG2_G(0),
137  QPLL0_CFG2_G3 => QPLL_CFG2_G3_G(0),
138  QPLL0_CFG3 => QPLL_CFG3_G(0),
139  QPLL0_CFG4 => QPLL_CFG4_G(0),
140  QPLL0_CP => QPLL_CP_G(0),
141  QPLL0_CP_G3 => QPLL_CP_G3_G(0),
142  QPLL0_FBDIV => QPLL_FBDIV_G(0),
143  QPLL0_FBDIV_G3 => QPLL_FBDIV_G3_G(0),
144  QPLL0_INIT_CFG0 => QPLL_INIT_CFG0_G(0),
145  QPLL0_INIT_CFG1 => QPLL_INIT_CFG1_G(0),
146  QPLL0_LOCK_CFG => QPLL_LOCK_CFG_G(0),
147  QPLL0_LOCK_CFG_G3 => QPLL_LOCK_CFG_G3_G(0),
148  QPLL0_LPF => QPLL_LPF_G(0),
149  QPLL0_LPF_G3 => QPLL_LPF_G3_G(0),
150  QPLL0_REFCLK_DIV => QPLL_REFCLK_DIV_G(0),
151  QPLL0_SDM_CFG0 => QPLL_SDM_CFG0_G(0),
152  QPLL0_SDM_CFG1 => QPLL_SDM_CFG1_G(0),
153  QPLL0_SDM_CFG2 => QPLL_SDM_CFG2_G(0),
154  QPLL1_CFG0 => QPLL_CFG0_G(1),
155  QPLL1_CFG1 => QPLL_CFG1_G(1),
156  QPLL1_CFG1_G3 => QPLL_CFG1_G3_G(1),
157  QPLL1_CFG2 => QPLL_CFG2_G(1),
158  QPLL1_CFG2_G3 => QPLL_CFG2_G3_G(1),
159  QPLL1_CFG3 => QPLL_CFG3_G(1),
160  QPLL1_CFG4 => QPLL_CFG4_G(1),
161  QPLL1_CP => QPLL_CP_G(1),
162  QPLL1_CP_G3 => QPLL_CP_G3_G(1),
163  QPLL1_FBDIV => QPLL_FBDIV_G(1),
164  QPLL1_FBDIV_G3 => QPLL_FBDIV_G3_G(1),
165  QPLL1_INIT_CFG0 => QPLL_INIT_CFG0_G(1),
166  QPLL1_INIT_CFG1 => QPLL_INIT_CFG1_G(1),
167  QPLL1_LOCK_CFG => QPLL_LOCK_CFG_G(1),
168  QPLL1_LOCK_CFG_G3 => QPLL_LOCK_CFG_G3_G(1),
169  QPLL1_LPF => QPLL_LPF_G(1),
170  QPLL1_LPF_G3 => QPLL_LPF_G3_G(1),
171  QPLL1_REFCLK_DIV => QPLL_REFCLK_DIV_G(1),
172  QPLL1_SDM_CFG0 => QPLL_SDM_CFG0_G(1),
173  QPLL1_SDM_CFG1 => QPLL_SDM_CFG1_G(1),
174  QPLL1_SDM_CFG2 => QPLL_SDM_CFG2_G(1),
175  RSVD_ATTR0 => x"0000",
176  RSVD_ATTR1 => x"0000",
177  RSVD_ATTR2 => x"0000",
178  RSVD_ATTR3 => x"0000",
179  RXRECCLKOUT0_SEL => "00",
180  RXRECCLKOUT1_SEL => "00",
181  SARC_EN => '1',
182  SARC_SEL => '0',
183  SDM0DATA1_0 => "0000000000000000",
184  SDM0DATA1_1 => "000000000",
185  SDM0INITSEED0_0 => "0000000000000000",
186  SDM0INITSEED0_1 => "000000000",
187  SDM0_DATA_PIN_SEL => '0',
188  SDM0_WIDTH_PIN_SEL => '0',
189  SDM1DATA1_0 => "0000000000000000",
190  SDM1DATA1_1 => "000000000",
191  SDM1INITSEED0_0 => "0000000000000000",
192  SDM1INITSEED0_1 => "000000000",
193  SDM1_DATA_PIN_SEL => '0',
194  SDM1_WIDTH_PIN_SEL => '0',
195  SIM_RESET_SPEEDUP => SIM_RESET_SPEEDUP_G,
196  SIM_VERSION => SIM_VERSION_G)
197  port map (
198  -- DRP Ports
199  DRPADDR => drpAddr,
200  DRPCLK => axilClk,
201  DRPDI => drpDi,
202  DRPDO => drpDo,
203  DRPEN => drpEn,
204  DRPRDY => drpRdy,
205  DRPWE => drpWe,
206  -- QPLL Outputs
207  PMARSVDOUT0 => open,
208  PMARSVDOUT1 => open,
209  QPLLDMONITOR0 => open,
210  QPLLDMONITOR1 => open,
211  REFCLKOUTMONITOR0 => open,
212  REFCLKOUTMONITOR1 => open,
213  RXRECCLK0_SEL => open,
214  RXRECCLK1_SEL => open,
215  QPLL0FBCLKLOST => qPllFbClkLost(0),
216  QPLL0LOCK => qPllLock(0),
217  QPLL0OUTCLK => qPllOutClk(0),
218  QPLL0OUTREFCLK => qPllOutRefClk(0),
219  QPLL0REFCLKLOST => qPllRefClkLost(0),
220  QPLL1FBCLKLOST => qPllFbClkLost(1),
221  QPLL1LOCK => qPllLock(1),
222  QPLL1OUTCLK => qPllOutClk(1),
223  QPLL1OUTREFCLK => qPllOutRefClk(1),
224  QPLL1REFCLKLOST => qPllRefClkLost(1),
225  -- QPLL Inputs
226  QPLL0CLKRSVD0 => '0',
227  QPLL0CLKRSVD1 => '0',
228  QPLL0LOCKDETCLK => qPllLockDetClk(0),
229  QPLL0LOCKEN => '1',
230  QPLL0PD => qPllPowerDown(0),
231  QPLL0REFCLKSEL => QPLL_REFCLK_SEL_G(0),
232  QPLL0RESET => qPllReset(0),
233  QPLL1CLKRSVD0 => '0',
234  QPLL1CLKRSVD1 => '0',
235  QPLL1LOCKDETCLK => qPllLockDetClk(1),
236  QPLL1LOCKEN => '1',
237  QPLL1PD => qPllPowerDown(1),
238  QPLL1REFCLKSEL => QPLL_REFCLK_SEL_G(1),
239  QPLL1RESET => qPllReset(1),
240  BGBYPASSB => '1',
241  BGMONITORENB => '1',
242  BGPDB => '1',
243  BGRCALOVRD => (others => '1'),
244  BGRCALOVRDENB => '1',
245  GTREFCLK00 => gtRefClk0(0),
246  GTREFCLK10 => gtRefClk1(0),
247  GTNORTHREFCLK00 => gtNorthRefClk0(0),
248  GTNORTHREFCLK10 => gtNorthRefClk1(0),
249  GTSOUTHREFCLK00 => gtSouthRefClk0(0),
250  GTSOUTHREFCLK10 => gtSouthRefClk1(0),
251  GTGREFCLK0 => gtGRefClk(0),
252  GTREFCLK01 => gtRefClk0(1),
253  GTREFCLK11 => gtRefClk1(1),
254  GTNORTHREFCLK01 => gtNorthRefClk0(1),
255  GTNORTHREFCLK11 => gtNorthRefClk1(1),
256  GTSOUTHREFCLK01 => gtSouthRefClk0(1),
257  GTSOUTHREFCLK11 => gtSouthRefClk1(1),
258  GTGREFCLK1 => gtGRefClk(1),
259  PMARSVD0 => (others => '0'),
260  PMARSVD1 => (others => '0'),
261  QPLLRSVD1 => (others => '0'),
262  QPLLRSVD2 => (others => '0'),
263  QPLLRSVD3 => (others => '0'),
264  QPLLRSVD4 => (others => '0'),
265  RCALENB => '1');
266 
267  U_AxiLiteToDrp : entity work.AxiLiteToDrp
268  generic map (
269  TPD_G => TPD_G,
270  AXI_ERROR_RESP_G => AXI_ERROR_RESP_G,
271  COMMON_CLK_G => true,
272  EN_ARBITRATION_G => false,
273  TIMEOUT_G => 4096,
274  ADDR_WIDTH_G => 9,
275  DATA_WIDTH_G => 16)
276  port map (
277  -- AXI-Lite Port
278  axilClk => axilClk,
279  axilRst => axilRst,
280  axilReadMaster => axilReadMaster,
281  axilReadSlave => axilReadSlave,
282  axilWriteMaster => axilWriteMaster,
283  axilWriteSlave => axilWriteSlave,
284  -- DRP Interface
285  drpClk => axilClk,
286  drpRst => axilRst,
287  drpRdy => drpRdy,
288  drpEn => drpEn,
289  drpWe => drpWe,
290  drpAddr => drpAddr,
291  drpDi => drpDi,
292  drpDo => drpDo);
293 
294 end architecture mapping;
GthUltraScaleQuadPll.QPLL_LPF_G3_G
QPLL_LPF_G3_GSlv10Array( 1 downto 0) :=( others => "1111111111")
Definition: GthUltraScaleQuadPll.vhd:63
AxiLiteToDrp.ADDR_WIDTH_G
ADDR_WIDTH_Gpositive range 1 to 32:= 16
Definition: AxiLiteToDrp.vhd:35
GthUltraScaleQuadPll.QPLL_CFG2_G
QPLL_CFG2_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:50
IprogUltraScale.ieee
_library_ ieeeieee
Definition: IprogUltraScale.vhd:19
GthUltraScaleQuadPll.QPLL_CFG1_G
QPLL_CFG1_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:48
StdRtlPkg.Slv3Array
array(natural range <> ) of slv( 2 downto 0) Slv3Array
Definition: StdRtlPkg.vhd:408
GthUltraScaleQuadPll.COMMON_CFG0_G
COMMON_CFG0_Gslv( 15 downto 0) := x"0000"
Definition: GthUltraScaleQuadPll.vhd:44
GthUltraScaleQuadPll.QPLL_CFG2_G3_G
QPLL_CFG2_G3_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:51
GthUltraScaleQuadPll.qPllOutClk
out qPllOutClkslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:72
GthUltraScaleQuadPll.QPLL_SDM_CFG2_G
QPLL_SDM_CFG2_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:67
GthUltraScaleQuadPll.QPLL_SDM_CFG1_G
QPLL_SDM_CFG1_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:66
AxiLiteToDrp.drpAddr
out drpAddrslv( ADDR_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:54
GthUltraScaleQuadPll.qPllLock
out qPllLockslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:75
AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111
GthUltraScaleQuadPll.BIAS_CFG1_G
BIAS_CFG1_Gslv( 15 downto 0) := x"0000"
Definition: GthUltraScaleQuadPll.vhd:39
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
GthUltraScaleQuadPll.SIM_RESET_SPEEDUP_G
SIM_RESET_SPEEDUP_Gstring := "FALSE"
Definition: GthUltraScaleQuadPll.vhd:33
AxiLiteToDrp.EN_ARBITRATION_G
EN_ARBITRATION_Gboolean := false
Definition: AxiLiteToDrp.vhd:33
AxiLiteToDrp.DATA_WIDTH_G
DATA_WIDTH_Gpositive range 1 to 32:= 16
Definition: AxiLiteToDrp.vhd:36
GthUltraScaleQuadPll.POR_CFG_G
POR_CFG_Gslv( 15 downto 0) := x"0004"
Definition: GthUltraScaleQuadPll.vhd:46
AxiLiteToDrp.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: AxiLiteToDrp.vhd:42
GthUltraScaleQuadPll.qPllReset
in qPllResetslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:79
AxiLiteToDrp.drpDo
in drpDoslv( DATA_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:56
AxiLiteToDrp.COMMON_CLK_G
COMMON_CLK_Gboolean := false
Definition: AxiLiteToDrp.vhd:32
GthUltraScaleQuadPll.qPllRefClk
in qPllRefClkslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:71
GthUltraScaleQuadPll.QPLL_LPF_G
QPLL_LPF_GSlv10Array( 1 downto 0) :=( others => "1111111111")
Definition: GthUltraScaleQuadPll.vhd:62
GthUltraScaleQuadPll.BIAS_CFG3_G
BIAS_CFG3_Gslv( 15 downto 0) := x"0040"
Definition: GthUltraScaleQuadPll.vhd:41
GthUltraScaleQuadPll.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: GthUltraScaleQuadPll.vhd:36
GthUltraScaleQuadPll.COMMON_CFG1_G
COMMON_CFG1_Gslv( 15 downto 0) := x"0000"
Definition: GthUltraScaleQuadPll.vhd:45
AxiLiteToDrp.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: AxiLiteToDrp.vhd:44
GthUltraScaleQuadPll.QPLL_LOCK_CFG_G
QPLL_LOCK_CFG_GSlv16Array( 1 downto 0) :=( others => x"01E8")
Definition: GthUltraScaleQuadPll.vhd:60
GthUltraScaleQuadPll.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: GthUltraScaleQuadPll.vhd:86
GthUltraScaleQuadPll.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: GthUltraScaleQuadPll.vhd:85
GthUltraScaleQuadPll.BIAS_CFG2_G
BIAS_CFG2_Gslv( 15 downto 0) := x"0000"
Definition: GthUltraScaleQuadPll.vhd:40
GthUltraScaleQuadPll.qPllLockDetClk
in qPllLockDetClkslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:76
AxiLitePkg.AXI_RESP_DECERR_C
slv( 1 downto 0) := "11" AXI_RESP_DECERR_C
Definition: AxiLitePkg.vhd:49
AxiLiteToDrp.axilReadMaster
in axilReadMasterAxiLiteReadMasterType
Definition: AxiLiteToDrp.vhd:41
GthUltraScaleQuadPll.QPLL_CFG4_G
QPLL_CFG4_GSlv16Array( 1 downto 0) :=( others => x"0009")
Definition: GthUltraScaleQuadPll.vhd:53
GthUltraScaleQuadPll.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: GthUltraScaleQuadPll.vhd:84
StdRtlPkg.NaturalArray
array(natural range <> ) of natural NaturalArray
Definition: StdRtlPkg.vhd:34
GthUltraScaleQuadPll.qPllFbClkLost
out qPllFbClkLostslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:74
AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59
GthUltraScaleQuadPll.QPLL_INIT_CFG1_G
QPLL_INIT_CFG1_GSlv8Array( 1 downto 0) :=( others => x"00")
Definition: GthUltraScaleQuadPll.vhd:59
GthUltraScaleQuadPll.qPllRefClkLost
out qPllRefClkLostslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:77
GthUltraScaleQuadPll.QPLL_CFG0_G
QPLL_CFG0_GSlv16Array( 1 downto 0) :=( others => x"3018")
Definition: GthUltraScaleQuadPll.vhd:47
GthUltraScaleQuadPll.QPLL_CFG1_G3_G
QPLL_CFG1_G3_GSlv16Array( 1 downto 0) :=( others => x"0020")
Definition: GthUltraScaleQuadPll.vhd:49
IprogUltraScale.unisim
_library_ unisimunisim
Definition: IprogUltraScale.vhd:26
AxiLiteToDrp.TIMEOUT_G
TIMEOUT_Gpositive := 4096
Definition: AxiLiteToDrp.vhd:34
GthUltraScaleQuadPll.QPLL_LOCK_CFG_G3_G
QPLL_LOCK_CFG_G3_GSlv16Array( 1 downto 0) :=( others => x"01E8")
Definition: GthUltraScaleQuadPll.vhd:61
GthUltraScaleQuadPll.qPllOutRefClk
out qPllOutRefClkslv( 1 downto 0)
Definition: GthUltraScaleQuadPll.vhd:73
StdRtlPkg.Slv16Array
array(natural range <> ) of slv( 15 downto 0) Slv16Array
Definition: StdRtlPkg.vhd:395
AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69
GthUltraScaleQuadPll.QPLL_FBDIV_G
QPLL_FBDIV_GNaturalArray( 1 downto 0) :=( others => 66)
Definition: GthUltraScaleQuadPll.vhd:56
GthUltraScaleQuadPll.BIAS_CFG_RSVD_G
BIAS_CFG_RSVD_Gslv( 9 downto 0) := "0000000000"
Definition: GthUltraScaleQuadPll.vhd:43
GthUltraScaleQuadPll.QPLL_CP_G
QPLL_CP_GSlv10Array( 1 downto 0) :=( others => "0000011111")
Definition: GthUltraScaleQuadPll.vhd:54
GthUltraScaleQuadPll.qPllPowerDown
in qPllPowerDownslv( 1 downto 0) := "00"
Definition: GthUltraScaleQuadPll.vhd:78
GthUltraScaleQuadPll.BIAS_CFG0_G
BIAS_CFG0_Gslv( 15 downto 0) := x"0000"
Definition: GthUltraScaleQuadPll.vhd:38
AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85
GthUltraScaleQuadPll.BIAS_CFG4_G
BIAS_CFG4_Gslv( 15 downto 0) := x"0000"
Definition: GthUltraScaleQuadPll.vhd:42
AxiLiteToDrp.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType
Definition: AxiLiteToDrp.vhd:43
AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125
AxiLiteToDrp.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: AxiLiteToDrp.vhd:31
GthUltraScaleQuadPll.QPLL_CP_G3_G
QPLL_CP_G3_GSlv10Array( 1 downto 0) :=( others => "0000011111")
Definition: GthUltraScaleQuadPll.vhd:55
AxiLiteToDrp.TPD_G
TPD_Gtime := 1 ns
Definition: AxiLiteToDrp.vhd:30
GthUltraScaleQuadPll.QPLL_CFG3_G
QPLL_CFG3_GSlv16Array( 1 downto 0) :=( others => x"0120")
Definition: GthUltraScaleQuadPll.vhd:52
GthUltraScaleQuadPll.axilReadMaster
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: GthUltraScaleQuadPll.vhd:83
GthUltraScaleQuadPll.QPLL_FBDIV_G3_G
QPLL_FBDIV_G3_GNaturalArray( 1 downto 0) :=( others => 80)
Definition: GthUltraScaleQuadPll.vhd:57
StdRtlPkg.Slv8Array
array(natural range <> ) of slv( 7 downto 0) Slv8Array
Definition: StdRtlPkg.vhd:403
GthUltraScaleQuadPll.QPLL_SDM_CFG0_G
QPLL_SDM_CFG0_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:65
GthUltraScaleQuadPll.QPLL_REFCLK_SEL_G
QPLL_REFCLK_SEL_GSlv3Array( 1 downto 0) :=( others => "001")
Definition: GthUltraScaleQuadPll.vhd:69
AxiLiteToDrp.drpDi
out drpDislv( DATA_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:55
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
StdRtlPkg.Slv10Array
array(natural range <> ) of slv( 9 downto 0) Slv10Array
Definition: StdRtlPkg.vhd:401
GthUltraScaleQuadPll.QPLL_INIT_CFG0_G
QPLL_INIT_CFG0_GSlv16Array( 1 downto 0) :=( others => x"0000")
Definition: GthUltraScaleQuadPll.vhd:58
GthUltraScaleQuadPll.QPLL_REFCLK_DIV_G
QPLL_REFCLK_DIV_GNaturalArray( 1 downto 0) :=( others => 2)
Definition: GthUltraScaleQuadPll.vhd:64