XauiGtyUltraScale.mapping Architecture Reference

Architecture >> XauiGtyUltraScale::mapping

Components
XauiGtyUltraScale156p25MHz10GigECore

Signals
phyRxd	slv ( 63 downto 0 )
phyRxc	slv ( 7 downto 0 )
phyTxd	slv ( 63 downto 0 )
phyTxc	slv ( 7 downto 0 )
phyClock	sl
phyClkBuf	sl
phyReset	sl
config	XauiConfig
status	XauiStatus
macRxAxisMaster	AxiStreamMasterType
macRxAxisCtrl	AxiStreamCtrlType
macTxAxisMaster	AxiStreamMasterType
macTxAxisSlave	AxiStreamSlaveType

Instantiations
u_mac	EthMacTop <Entity EthMacTop>
u_xauigtyultrascalecore	xauigtyultrascale156p25mhz10gigecore
rstsync_inst	RstSync <Entity RstSync>
u_xauireg	XauiReg <Entity XauiReg>

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The documentation for this design unit was generated from the following file:

• ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd