XauiGth7.mapping Architecture Reference

Architecture >> XauiGth7::mapping

Signals
phyRxd	slv ( 63 downto 0 )
phyRxc	slv ( 7 downto 0 )
phyTxd	slv ( 63 downto 0 )
phyTxc	slv ( 7 downto 0 )
areset	sl
phyClock	sl
phyReset	sl
config	XauiConfig
status	XauiStatus
macRxAxisMaster	AxiStreamMasterType
macRxAxisCtrl	AxiStreamCtrlType
macTxAxisMaster	AxiStreamMasterType
macTxAxisSlave	AxiStreamSlaveType

Instantiations
u_mac	EthMacTop <Entity EthMacTop>
u_xauigth7core	XauiGth7Core <Entity XauiGth7Core>
rstsync_0	RstSync <Entity RstSync>
rstsync_1	RstSync <Entity RstSync>
u_xauireg	XauiReg <Entity XauiReg>

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The documentation for this design unit was generated from the following file:

• ethernet/XauiCore/gth7/rtl/XauiGth7.vhd