TenGigEthGth7Wrapper.mapping Architecture Reference

Architecture >> TenGigEthGth7Wrapper::mapping

Signals
phyClock	sl
phyReset	sl
qplllock	sl
qplloutclk	sl
qplloutrefclk	sl
qpllRst	slv ( NUM_LANE_G- 1 downto 0 )
qpllReset	sl

Instantiations
tengigethgth7clk_inst	TenGigEthGth7Clk <Entity TenGigEthGth7Clk>
tengigethgth7_inst	TenGigEthGth7 <Entity TenGigEthGth7>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd