TenGigEthGth7 Entity Reference

Inheritance diagram for TenGigEthGth7:

Collaboration diagram for TenGigEthGth7:

Entities
TenGigEthGth7.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
TenGigEthPkg	Package <TenGigEthPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
EN_AXI_REG_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk	in	sl
dmaRst	in	sl
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
axiLiteClk	in	sl := ' 0 '
axiLiteRst	in	sl := ' 0 '
axiLiteReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave	out	AxiLiteReadSlaveType
axiLiteWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave	out	AxiLiteWriteSlaveType
sigDet	in	sl := ' 1 '
txFault	in	sl := ' 0 '
txDisable	out	sl
extRst	in	sl
phyClk	in	sl
phyRst	in	sl
phyReady	out	sl
qplllock	in	sl
qplloutclk	in	sl
qplloutrefclk	in	sl
qpllRst	out	sl
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd