SugoiTopTb.testbed Architecture Reference

Architecture >> SugoiTopTb::testbed

Processes
gen_trig_traffic
test

Constants
NUM_SUB_C	positive := 4
NUM_ADDR_BITS_C	positive := 28
ADDR_STRIDE_C	positive := ( 2 ** NUM_ADDR_BITS_C )
CLK_PERIOD_G	time := 10 ns
TPD_G	time := CLK_PERIOD_G/ 4

Signals
axilClk	sl := ' 0 '
axilRst	sl := ' 0 '
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
clkInP	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 0 ' )
clkInN	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 1 ' )
clkOutP	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 0 ' )
clkOutN	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 1 ' )
rxP	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 0 ' )
rxN	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 1 ' )
txP	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 0 ' )
txN	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 1 ' )
linkup	slv ( NUM_SUB_C downto 0 ) := ( others = > ' 0 ' )
globalRst	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 0 ' )
globalRstL	slv ( NUM_SUB_C- 1 downto 0 ) := ( others = > ' 0 ' )
opCode	Slv8Array ( NUM_SUB_C- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
opCodeBit	sl := ' 0 '
opCodeBitSel	natural := 0
manGlobalRst	sl := ' 0 '
manOpCode	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
manOpCodeMask	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
manStrobe	sl := ' 0 '
startTrigTraffic	sl := ' 0 '
trafficOpCode	slv ( 7 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_simmodel	SugoiSubordinateSimModel <Entity SugoiSubordinateSimModel>
u_manager	SugoiManagerCore <Entity SugoiManagerCore>

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The documentation for this design unit was generated from the following file:

• protocols/sugoi/tb/SugoiTb.vhd