SsiPrbsTb.testbed Architecture Reference

Architecture >> SsiPrbsTb::testbed

Functions
AxiStreamConfigType	PrbsAxiStreamConfig ( dataBytes: in natural , tKeepMode: in TKeepModeType TKEEP_COMP_C )
AxiStreamConfigType	PrbsAxiStreamConfig ( dataBytes: in natural , tKeepMode: in TKeepModeType TKEEP_COMP_C )

Processes
PROCESS_161	( slowClk )
PROCESS_162	( failed , passed )
PROCESS_367	( slowClk )
PROCESS_368	( failed , passed )

Constants
SLOW_CLK_PERIOD_C	time := 10 ns
FAST_CLK_PERIOD_C	time := SLOW_CLK_PERIOD_C/ 3
TPD_C	time := FAST_CLK_PERIOD_C/ 4
STATUS_CNT_WIDTH_C	natural := 32
TX_PACKET_LENGTH_C	slv ( 31 downto 0 ) := toSlv ( 256 , 32 )
NUMBER_PACKET_C	slv ( 31 downto 0 ) := x " 00000FFF "
MEMORY_TYPE_C	string := " block "
GEN_SYNC_FIFO_C	boolean := false
CASCADE_SIZE_C	natural := 1
FIFO_ADDR_WIDTH_C	natural := 9
FIFO_PAUSE_THRESH_C	natural := 2 ** 8
PRBS_SEED_SIZE_C	natural := 32
PRBS_TAPS_C	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
FORCE_EOFE_C	sl := ' 0 '
AXI_STREAM_CONFIG_C	AxiStreamConfigType := PrbsAxiStreamConfig ( 16 , TKEEP_COMP_C )
AXI_PIPE_STAGES_C	natural := 1

Signals
fastClk	sl := ' 0 '
slowClk	sl := ' 0 '
errMissedPacket	sl := ' 0 '
errLength	sl := ' 0 '
errDataBus	sl := ' 0 '
errEofe	sl := ' 0 '
passed	sl := ' 0 '
failed	sl := ' 0 '
updated	sl := ' 0 '
fastRst	sl := ' 1 '
slowRst	sl := ' 1 '
errWordCnt	slv ( 31 downto 0 )
errbitCnt	slv ( 31 downto 0 )
cnt	slv ( 31 downto 0 )
axisMaster	AxiStreamMasterType
axisSlave	AxiStreamSlaveType

Instantiations
clkrst_fast	ClkRst <Entity ClkRst>
clkrst_slow	ClkRst <Entity ClkRst>
ssiprbstx_inst	SsiPrbsTx <Entity SsiPrbsTx>
ssiprbsrx_inst	SsiPrbsRx <Entity SsiPrbsRx>
clkrst_fast	ClkRst <Entity ClkRst>
clkrst_slow	ClkRst <Entity ClkRst>
ssiprbstx_inst	SsiPrbsTx <Entity SsiPrbsTx>
ssiprbsrx_inst	SsiPrbsRx <Entity SsiPrbsRx>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiPrbsTb.vhd
• protocols/ssi/tb/SsiPrbsTb.vhd