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Constants | Instantiations | Processes | Records | Signals | Types
SrpV3AxiTb.tb Architecture Reference
Architecture >> SrpV3AxiTb::tb

Processes

comb  ( r , rst , rxMaster , txSlave )
seq  ( clk )
PROCESS_163  ( failed , passed )
comb  ( r , rst , rxMaster , txSlave )
seq  ( clk )
PROCESS_369  ( failed , passed )

Constants

FSM_AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
SRP_AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
AXI_CONFIG_C  AxiConfigType := ( ADDR_WIDTH_C = > 12 , DATA_BYTES_C = > 8 , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )
REQ_BYTE_SIZE_C  positive := ( 2 ** AXI_CONFIG_C.ADDR_WIDTH_C )
REQ_WORD_SIZE_C  positive := ( REQ_BYTE_SIZE_C/ 4 )
CLK_PERIOD_C  time := 10 ns
TPD_G  time := ( CLK_PERIOD_C/ 4 )
REG_INIT_C  RegType := ( opCode = > x " 02 " , cnt = > 0 , tid = > x " 1234_0000 " , addr = > ( others = > ' 0 ' ) , txMaster = > AXI_STREAM_MASTER_INIT_C , rxSlave = > AXI_STREAM_SLAVE_INIT_C , state = > REQ_MSG , passed = > ' 0 ' , failed = > ' 0 ' )

Types

StateType  ( REQ_MSG , TX_PAYLOAD , RX_HDR , RX_PAYLOAD , FAILED_S , PASSED_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
clk  sl := ' 0 '
rst  sl := ' 1 '
axiWriteMaster  AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave  AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiReadMaster  AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave  AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
srpIbMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srpIbSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
srpObMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srpObSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
txMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rxMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
passed  sl := ' 0 '
failed  sl := ' 0 '

Records

RegType 

Instantiations

u_clkrst  ClkRst <Entity ClkRst>
u_mem  AxiRam <Entity AxiRam>
u_srpv3  SrpV3Axi <Entity SrpV3Axi>
u_tx  AxiStreamResize <Entity AxiStreamResize>
u_rx  AxiStreamResize <Entity AxiStreamResize>
u_clkrst  ClkRst <Entity ClkRst>
u_mem  AxiRam <Entity AxiRam>
u_srpv3  SrpV3Axi <Entity SrpV3Axi>
u_tx  AxiStreamResize <Entity AxiStreamResize>
u_rx  AxiStreamResize <Entity AxiStreamResize>
The documentation for this design unit was generated from the following files: