Architecture >> SrpV0LoopbackWrapper::rtl

Constants
TPD_C	time := 10 ns/ 4
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 )

Signals
axilClk	sl := ' 0 '
axilRst	sl := ' 1 '
uutAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
uutAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
uutAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
uutAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
srpAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
srpAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
srpAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
srpAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
txAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rxAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations
u_shimlayerslave	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axilitesrpv0	AxiLiteSrpV0 <Entity AxiLiteSrpV0>
u_srpv0axilite	SrpV0AxiLite <Entity SrpV0AxiLite>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>

The documentation for this design unit was generated from the following file:

Constants

Signals