SelectioDeserUltraScale.mapping Architecture Reference

Architecture >> SelectioDeserUltraScale::mapping

Signals
drpRdy	sl
drpEn	sl
drpWe	sl
drpAddr	slv ( 6 downto 0 )
drpDi	slv ( 15 downto 0 )
drpDo	slv ( 15 downto 0 )
locked	sl := ' 0 '
clkFb	sl := ' 0 '
clkout0	sl := ' 0 '
clkout1	sl := ' 0 '
clkx4	sl := ' 0 '
clkx1	sl := ' 0 '
reset	sl := ' 1 '
rstx1	sl := ' 1 '

Instantiations
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>
u_pll	plle3_adv
u_clkout0	ClkRst <Entity ClkRst>
u_clkout1	ClkRst <Entity ClkRst>
u_bufg640	bufg
u_userclk	bufg
u_bufg	bufgce_div
u_reset	RstSync <Entity RstSync>
u_rstx1	RstPipeline <Entity RstPipeline>
u_lane	SelectioDeserLaneUltraScale <Entity SelectioDeserLaneUltraScale>

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd