ScramblerTb.testbed Architecture Reference

Architecture >> ScramblerTb::testbed

Processes
PROCESS_156	( clk )
PROCESS_157	( failedDly )
PROCESS_268	( clk )
PROCESS_269	( failedDly )

Constants
TPD_C	time := 1 ns
CLK_PERIOD_C	time := 10 ns
EN_SCRAMBLING_C	sl := ' 1 '

Signals
clk	sl := ' 0 '
rst	sl := ' 0 '
rxValid	sl := ' 0 '
rxValidDly	sl := ' 0 '
rxData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
rxDataDly	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
txData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
sync	sl := ' 0 '
sysref	sl := ' 0 '
lmfc	sl := ' 0 '
rxGt	jesdGtRxLaneType := JESD_GT_RX_LANE_INIT_C
txGt	jesdGtTxLaneType := JESD_GT_TX_LANE_INIT_C
cnt	slv ( 31 downto 0 ) := toSlv ( 1 , 32 )
failed	sl := ' 0 '
failedDly	sl := ' 0 '

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_sync	JesdLmfcGen <Entity JesdLmfcGen>
u_lmfcgen	JesdLmfcGen <Entity JesdLmfcGen>
u_tx	JesdTxLane <Entity JesdTxLane>
u_rx	JesdRxLane <Entity JesdRxLane>
u_clkrst	ClkRst <Entity ClkRst>
u_sync	JesdLmfcGen <Entity JesdLmfcGen>
u_lmfcgen	JesdLmfcGen <Entity JesdLmfcGen>
u_tx	JesdTxLane <Entity JesdTxLane>
u_rx	JesdRxLane <Entity JesdRxLane>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/ScramblerTb.vhd
• protocols/jesd204b/sim/ScramblerTb.vhd