SaltTxLvds.rtl Architecture Reference

Architecture >> SaltTxLvds::rtl

Processes
comb	( r , rst125MHz , txData , txEn )
seq	( clk125MHz )

Constants
REG_INIT_C	RegType := ( txData = > ( others = > ' 0 ' ) , dataK = > ' 1 ' , data = > K_28_5_C , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S , TERM_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
data10b	slv ( 9 downto 0 )
data8b	slv ( 7 downto 0 )

Records
RegType

Instantiations
u_encoder	Encoder8b10b <Entity Encoder8b10b>
u_gearbox	AsyncGearbox <Entity AsyncGearbox>
u_txser	SaltTxSer <Entity SaltTxSer>

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The documentation for this design unit was generated from the following file:

• protocols/salt/rtl/SaltTxLvds.vhd