SaltTxSer Entity Reference

Inheritance diagram for SaltTxSer:

Entities
SaltTxSer.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_DEVICE_G	string := " 7SERIES "

Ports
txP	out	sl
txN	out	sl
clkx4	in	sl
clkx1	in	sl
rstx1	in	sl
dataIn	in	slv ( 7 downto 0 )

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The documentation for this design unit was generated from the following files:

• protocols/salt/rtl/7Series/SaltTxSer.vhd
• protocols/salt/rtl/UltraScale/SaltTxSer.vhd