Architecture >> RssiCoreIntegrationWrapper::mapping

Processes
cltSAppComb	( cltSAppEofe , cltSAppSof , cltSAppTData , cltSAppTKeep , cltSAppTLast , cltSAppTValid )
srvSAppComb	( srvSAppEofe , srvSAppSof , srvSAppTData , srvSAppTKeep , srvSAppTLast , srvSAppTValid )
cltSTspComb	( cltSTspEofe , cltSTspSof , cltSTspTData , cltSTspTKeep , cltSTspTLast , cltSTspTValid )
srvSTspComb	( srvSTspEofe , srvSTspSof , srvSTspTData , srvSTspTKeep , srvSTspTLast , srvSTspTValid )

Signals
axilRstN	sl
cltSAppMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
cltSAppSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
cltMAppMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
cltMAppSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
srvSAppMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srvSAppSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
srvMAppMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srvMAppSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
cltTspMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
cltTspSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
srvTspMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srvTspSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
cltRxTspMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
cltRxTspSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
srvRxTspMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
srvRxTspSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
cltAxilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
cltAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
cltAxilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
cltAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
srvAxilReadSlave	AxiLiteReadSlaveType
srvAxilWriteSlave	AxiLiteWriteSlaveType
cltStatusReg	slv ( 8 downto 0 )
srvStatusReg	slv ( 8 downto 0 )

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_client	RssiCore <Entity RssiCore>
u_server	RssiCore <Entity RssiCore>

The documentation for this design unit was generated from the following file:

Processes

Signals