RssiCoreIntegrationWrapper Entity Reference

Inheritance diagram for RssiCoreIntegrationWrapper:

Collaboration diagram for RssiCoreIntegrationWrapper:

Entities
RssiCoreIntegrationWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
SsiPkg	Package <SsiPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
RssiPkg	Package <RssiPkg>

Generics
TPD_G	time := 1 ns
CLK_FREQUENCY_G	real := 1 . 0E6
TIMEOUT_UNIT_G	real := 1 . 0E - 6
WINDOW_ADDR_SIZE_G	positive := 2
SEGMENT_ADDR_SIZE_G	positive := 5
MAX_NUM_OUTS_SEG_G	positive := 4
MAX_SEG_SIZE_G	positive := 32
ACK_TOUT_G	positive := 4
RETRANS_TOUT_G	positive := 16
NULL_TOUT_G	positive := 48
MAX_RETRANS_CNT_G	positive := 2
MAX_CUM_ACK_CNT_G	positive := 2
CLIENT_INIT_SEQ_N_G	natural := 16#20#
SERVER_INIT_SEQ_N_G	natural := 16#80#
CONN_ID_G	positive := 16#12345678#
VERSION_G	positive := 1
HEADER_CHKSUM_EN_G	boolean := true
RETRANSMIT_ENABLE_G	boolean := true

Ports
axisClk	in	sl
axisRst	in	sl
cltOpen_i	in	sl
cltClose_i	in	sl
cltInject_i	in	sl
srvOpen_i	in	sl
srvClose_i	in	sl
srvInject_i	in	sl
cltSAppTValid	in	sl
cltSAppTReady	out	sl
cltSAppTData	in	slv ( 63 downto 0 )
cltSAppTKeep	in	slv ( 7 downto 0 )
cltSAppTLast	in	sl
cltSAppSof	in	sl
cltSAppEofe	in	sl
cltMAppTValid	out	sl
cltMAppTReady	in	sl
cltMAppTData	out	slv ( 63 downto 0 )
cltMAppTKeep	out	slv ( 7 downto 0 )
cltMAppTLast	out	sl
cltMAppSof	out	sl
cltMAppEofe	out	sl
srvSAppTValid	in	sl
srvSAppTReady	out	sl
srvSAppTData	in	slv ( 63 downto 0 )
srvSAppTKeep	in	slv ( 7 downto 0 )
srvSAppTLast	in	sl
srvSAppSof	in	sl
srvSAppEofe	in	sl
srvMAppTValid	out	sl
srvMAppTReady	in	sl
srvMAppTData	out	slv ( 63 downto 0 )
srvMAppTKeep	out	slv ( 7 downto 0 )
srvMAppTLast	out	sl
srvMAppSof	out	sl
srvMAppEofe	out	sl
cltSTspTValid	in	sl
cltSTspTReady	out	sl
cltSTspTData	in	slv ( 63 downto 0 )
cltSTspTKeep	in	slv ( 7 downto 0 )
cltSTspTLast	in	sl
cltSTspSof	in	sl
cltSTspEofe	in	sl
cltMTspTValid	out	sl
cltMTspTReady	in	sl
cltMTspTData	out	slv ( 63 downto 0 )
cltMTspTKeep	out	slv ( 7 downto 0 )
cltMTspTLast	out	sl
cltMTspSof	out	sl
cltMTspEofe	out	sl
srvSTspTValid	in	sl
srvSTspTReady	out	sl
srvSTspTData	in	slv ( 63 downto 0 )
srvSTspTKeep	in	slv ( 7 downto 0 )
srvSTspTLast	in	sl
srvSTspSof	in	sl
srvSTspEofe	in	sl
srvMTspTValid	out	sl
srvMTspTReady	in	sl
srvMTspTData	out	slv ( 63 downto 0 )
srvMTspTKeep	out	slv ( 7 downto 0 )
srvMTspTLast	out	sl
srvMTspSof	out	sl
srvMTspEofe	out	sl
S_AXI_AWADDR	in	slv ( 9 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 9 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
cltStatusReg_o	out	slv ( 8 downto 0 )
srvStatusReg_o	out	slv ( 8 downto 0 )
cltConnected_o	out	sl
srvConnected_o	out	sl
cltMaxSegSize_o	out	slv ( 15 downto 0 )
srvMaxSegSize_o	out	slv ( 15 downto 0 )

---

The documentation for this design unit was generated from the following file:

• protocols/rssi/v1/wrappers/RssiCoreIntegrationWrapper.vhd