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RoCEv2DcqcnWrapper.rtl Architecture Reference
Architecture >> RoCEv2DcqcnWrapper::rtl

Processes

sAxisComb  ( S_AXIS_TVALID , S_AXIS_TDATA , S_AXIS_TKEEP , S_AXIS_TLAST )

Signals

axilClk  sl
axilRst  sl
axilReadMaster  AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave  AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster  AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave  AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations

u_shimlayer  SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut  RoCEv2Dcqcn <Entity RoCEv2Dcqcn>

The documentation for this design unit was generated from the following file: