Architecture >> RoCEv2AxiStreamRdmaCoreWrapper::rtl

Processes
sAxisComb	( S_AXIS_TVALID , S_AXIS_TDATA , S_AXIS_TKEEP , S_AXIS_TLAST )
dmaReadReqComb	( S_DMAREADREQ_VALID , S_DMAREADREQ_INITIATOR , S_DMAREADREQ_SQPN , S_DMAREADREQ_WRID , S_DMAREADREQ_STARTADDR , S_DMAREADREQ_LEN , S_DMAREADREQ_MRIDX )
workCompComb	( S_WORKCOMP_VALID , S_WORKCOMP_STATUS , S_WORKCOMP_ID )

Signals
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
dmaReadReqMaster	RoCEv2DmaReadReqMasterType := ROCE_DMA_READ_REQ_MASTER_INIT_C
dmaReadReqSlave	RoCEv2DmaReadReqSlaveType := ROCE_DMA_READ_REQ_SLAVE_INIT_C
dmaReadRespMaster	RoCEv2DmaReadRespMasterType := ROCE_DMA_READ_RESP_MASTER_INIT_C
dmaReadRespSlave	RoCEv2DmaReadRespSlaveType := ROCE_DMA_READ_RESP_SLAVE_INIT_C
workReqMaster	RoCEv2WorkReqMasterType := ROCE_WORK_REQ_MASTER_INIT_C
workReqSlave	RoCEv2WorkReqSlaveType := ROCE_WORK_REQ_SLAVE_INIT_C
workCompMaster	RoCEv2WorkCompMasterType := ROCE_WORK_COMP_MASTER_INIT_C
workCompSlave	RoCEv2WorkCompSlaveType := ROCE_WORK_COMP_SLAVE_INIT_C

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	RoCEv2AxiStreamRdmaCore <Entity RoCEv2AxiStreamRdmaCore>

The documentation for this design unit was generated from the following file:

Processes

Signals