RoCEv2AxiStreamRdmaCoreWrapper Entity Reference

Inheritance diagram for RoCEv2AxiStreamRdmaCoreWrapper:

Collaboration diagram for RoCEv2AxiStreamRdmaCoreWrapper:

Entities
RoCEv2AxiStreamRdmaCoreWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
RoCEv2Pkg	Package <RoCEv2Pkg>

Generics
TPD_G	time := 1 ns

Ports
clk	in	sl
rst	in	sl
S_AXIS_TVALID	in	sl
S_AXIS_TDATA	in	slv ( 255 downto 0 )
S_AXIS_TKEEP	in	slv ( 31 downto 0 )
S_AXIS_TLAST	in	sl
S_AXIS_TREADY	out	sl
M_WORKREQ_VALID	out	sl
M_WORKREQ_READY	in	sl
M_WORKREQ_ID	out	slv ( 63 downto 0 )
M_WORKREQ_OPCODE	out	slv ( 3 downto 0 )
M_WORKREQ_FLAGS	out	slv ( 4 downto 0 )
M_WORKREQ_RADDR	out	slv ( 63 downto 0 )
M_WORKREQ_RKEY	out	slv ( 31 downto 0 )
M_WORKREQ_LEN	out	slv ( 31 downto 0 )
M_WORKREQ_SQPN	out	slv ( 23 downto 0 )
M_WORKREQ_IMMDT	out	slv ( 32 downto 0 )
S_DMAREADREQ_VALID	in	sl
S_DMAREADREQ_READY	out	sl
S_DMAREADREQ_INITIATOR	in	slv ( 3 downto 0 )
S_DMAREADREQ_SQPN	in	slv ( 23 downto 0 )
S_DMAREADREQ_WRID	in	slv ( 63 downto 0 )
S_DMAREADREQ_STARTADDR	in	slv ( 63 downto 0 )
S_DMAREADREQ_LEN	in	slv ( 12 downto 0 )
S_DMAREADREQ_MRIDX	in	sl
M_DMAREADRESP_VALID	out	sl
M_DMAREADRESP_READY	in	sl
M_DMAREADRESP_DATASTREAM	out	slv ( 289 downto 0 )
M_DMAREADRESP_ISRESPERR	out	sl
M_DMAREADRESP_WRID	out	slv ( 63 downto 0 )
M_DMAREADRESP_SQPN	out	slv ( 23 downto 0 )
M_DMAREADRESP_INITIATOR	out	slv ( 3 downto 0 )
S_WORKCOMP_VALID	in	sl
S_WORKCOMP_READY	out	sl
S_WORKCOMP_STATUS	in	slv ( 4 downto 0 )
S_WORKCOMP_ID	in	slv ( 63 downto 0 )
S_AXIL_AWADDR	in	slv ( 31 downto 0 )
S_AXIL_AWPROT	in	slv ( 2 downto 0 )
S_AXIL_AWVALID	in	sl
S_AXIL_AWREADY	out	sl
S_AXIL_WDATA	in	slv ( 31 downto 0 )
S_AXIL_WSTRB	in	slv ( 3 downto 0 )
S_AXIL_WVALID	in	sl
S_AXIL_WREADY	out	sl
S_AXIL_BRESP	out	slv ( 1 downto 0 )
S_AXIL_BVALID	out	sl
S_AXIL_BREADY	in	sl
S_AXIL_ARADDR	in	slv ( 31 downto 0 )
S_AXIL_ARPROT	in	slv ( 2 downto 0 )
S_AXIL_ARVALID	in	sl
S_AXIL_ARREADY	out	sl
S_AXIL_RDATA	out	slv ( 31 downto 0 )
S_AXIL_RRESP	out	slv ( 1 downto 0 )
S_AXIL_RVALID	out	sl
S_AXIL_RREADY	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/wrappers/RoCEv2AxiStreamRdmaCoreWrapper.vhd