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PgpRxVcFifoWrapper.rtl Architecture Reference
Architecture >> PgpRxVcFifoWrapper::rtl

Constants

TUSER_WIDTH_C  positive := 1
TID_WIDTH_C  positive := 1
TDEST_WIDTH_C  positive := 1
TDATA_NUM_BYTES_C  positive := 8

Signals

pgpAResetN  sl := ' 1 '
axisAResetN  sl := ' 1 '
sAxisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mAxisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
pgpRxCtrlInt  AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
pgpRxSlaveInt  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations

u_shimlayerslave  SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_dut  PgpRxVcFifo <Entity PgpRxVcFifo>
u_shimlayermaster  MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>

The documentation for this design unit was generated from the following file: