Pgp4RxLiteLowSpeedRegWrapper.rtl Architecture Reference

Architecture >> Pgp4RxLiteLowSpeedRegWrapper::rtl

Signals
eyeWidth	Slv9Array ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
dlyConfig	Slv9Array ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
usrDlyCfg	Slv9Array ( 1 downto 0 )
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_sh	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	Pgp4RxLiteLowSpeedReg <Entity Pgp4RxLiteLowSpeedReg>

---

The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd