Pgp4RxLiteLowSpeedRegWrapper Entity Reference

Inheritance diagram for Pgp4RxLiteLowSpeedRegWrapper:

Collaboration diagram for Pgp4RxLiteLowSpeedRegWrapper:

Entities
Pgp4RxLiteLowSpeedRegWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Ports
deserClk	in	sl
deserRst	in	sl
errorDet	in	slv ( 1 downto 0 )
bitSlip	in	slv ( 1 downto 0 )
locked	in	slv ( 1 downto 0 )
polarityOut	out	slv ( 1 downto 0 )
bitOrderOut	out	slv ( 1 downto 0 )
enUsrDlyCfgOut	out	sl
lane0UsrDlyCfg	out	slv ( 8 downto 0 )
lane1UsrDlyCfg	out	slv ( 8 downto 0 )
S_AXI_ACLK	in	std_logic := ' 0 '
S_AXI_ARESETN	in	std_logic := ' 0 '
S_AXI_AWADDR	in	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
S_AXI_AWVALID	in	std_logic := ' 0 '
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' )
S_AXI_WVALID	in	std_logic := ' 0 '
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic := ' 0 '
S_AXI_ARADDR	in	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
S_AXI_ARVALID	in	std_logic := ' 0 '
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic := ' 0 '

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd