Pgp3GtyUsIpWrapper.mapping Architecture Reference

Architecture >> Pgp3GtyUsIpWrapper::mapping

Processes
PROCESS_357	( txUsrClk2Int )
PROCESS_358	( rxUsrClk2Int )

Components
Pgp3GtyUsIp25G
Pgp3GtyUsIp20G
Pgp3GtyUsIp18G
Pgp3GtyUsIp17G
Pgp3GtyUsIp15G
Pgp3GtyUsIp13G
Pgp3GtyUsIp12G
Pgp3GtyUsIp10G
Pgp3GtyUsIp6G
Pgp3GtyUsIp3G

Signals
dummy1	sl
dummy2	sl
dummy3	slv ( 3 downto 0 )
dummy4	sl
dummy5	sl
dummy6	sl
dummy7	sl
dummy8	sl
dummy9	sl
dummy10	sl
dummy11	sl
zeroBit	sl
txsequence_in	slv ( 6 downto 0 ) := ( others = > ' 0 ' )
txheader_in	slv ( 5 downto 0 ) := ( others = > ' 0 ' )
rxUsrClk2Int	sl := ' 0 '
rxUsrClkActiveInt	sl := ' 0 '
txUsrClk2Int	sl := ' 0 '
txUsrClkActiveInt	sl := ' 0 '
drpAddr	slv ( 9 downto 0 ) := ( others = > ' 0 ' )
drpDi	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpEn	sl := ' 0 '
drpWe	sl := ' 0 '
drpRdy	sl := ' 0 '
rxUsrClkReset	sl := ' 0 '
txUsrClkReset	sl := ' 0 '
rxGearboxSlipInt	sl := ' 0 '
rxDataValidInt	sl := ' 0 '
rxHeaderValidInt	sl := ' 0 '
txHeaderInt	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
txDataInt	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
rxHeaderInt	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
rxDataInt	slv ( 63 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_rstsync_tx	RstSync <Entity RstSync>
u_rstsync_rx	RstSync <Entity RstSync>
u_fec	Pgp4GtyUsIpFecWrapper <Entity Pgp4GtyUsIpFecWrapper>
u_pgp3gtyusip	pgp3gtyusip25g
u_pgp3gtyusip	pgp3gtyusip20g
u_pgp3gtyusip	pgp3gtyusip18g
u_pgp3gtyusip	pgp3gtyusip17g
u_pgp3gtyusip	pgp3gtyusip15g
u_pgp3gtyusip	pgp3gtyusip13g
u_pgp3gtyusip	pgp3gtyusip12g
u_pgp3gtyusip	pgp3gtyusip10g
u_pgp3gtyusip	pgp3gtyusip6g
u_pgp3gtyusip	pgp3gtyusip3g
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsIpWrapper.vhd