Pgp3GtyUsIpWrapper Entity Reference

Inheritance diagram for Pgp3GtyUsIpWrapper:

Collaboration diagram for Pgp3GtyUsIpWrapper:

Entities
Pgp3GtyUsIpWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
EN_DRP_G	boolean := true
EN_FEC_G	boolean := false
RATE_G	string := " 10.3125Gbps "

Ports
stableClk	in	sl
stableRst	in	sl
qpllLock	in	slv ( 1 downto 0 )
qpllclk	in	slv ( 1 downto 0 )
qpllrefclk	in	slv ( 1 downto 0 )
qpllRst	out	slv ( 1 downto 0 ) := " 00 "
gtRxP	in	sl
gtRxN	in	sl
gtTxP	out	sl
gtTxN	out	sl
rxReset	in	sl
rxUsrClkActive	out	sl
rxResetDone	out	sl
rxUsrClk	out	sl
rxUsrClk2	out	sl
rxUsrClkRst	out	sl
rxData	out	slv ( 63 downto 0 )
rxDataValid	out	sl
rxHeader	out	slv ( 1 downto 0 )
rxHeaderValid	out	sl
rxBypassFec	in	sl := ' 0 '
rxFecInjErr	in	sl := ' 0 '
rxFecLock	out	sl
rxFecCorInc	out	sl
rxFecUnCorInc	out	sl
rxStartOfSeq	out	sl
rxGearboxSlip	in	sl
rxOutClk	out	sl
rxPolarity	in	sl
txReset	in	sl
txUsrClkActive	out	sl
txResetDone	out	sl
txUsrClk	out	sl
txUsrClk2	out	sl
txUsrClkRst	out	sl
txData	in	slv ( 63 downto 0 )
txHeader	in	slv ( 1 downto 0 )
txBypassFec	in	sl := ' 0 '
txOutClk	out	sl
loopback	in	slv ( 2 downto 0 )
txDiffCtrl	in	slv ( 4 downto 0 )
txPreCursor	in	slv ( 4 downto 0 )
txPostCursor	in	slv ( 4 downto 0 )
txPolarity	in	sl
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsIpWrapper.vhd