Architecture >> Pgp3Gtp7::rtl

Constants
NUM_AXIL_MASTERS_C	integer := 2
PGP_AXIL_INDEX_C	integer := 0
DRP_AXIL_INDEX_C	integer := 1
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( PGP_AXIL_INDEX_C = > ( baseAddr = > AXIL_BASE_ADDR_G , addrBits = > 12 , connectivity = > X " FFFF " ) , DRP_AXIL_INDEX_C = > ( baseAddr = > AXIL_BASE_ADDR_G+ X " 1000 " , addrBits = > 11 , connectivity = > X " FFFF " ) )

Signals
phyRxClk	sl := ' 0 '
phyRxRst	sl := ' 1 '
phyTxClk	sl := ' 0 '
phyTxRst	sl := ' 1 '
phyRxInit	sl := ' 0 '
phyRxActive	sl := ' 0 '
phyRxValid	sl := ' 0 '
phyRxHeader	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
phyRxData	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyRxSlip	sl := ' 0 '
locRxOut	Pgp3RxOutType
phyTxActive	sl := ' 0 '
phyTxHeader	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
phyTxData	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyTxValid	sl := ' 0 '
phyTxDataRdy	sl := ' 0 '
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )
loopback	slv ( 2 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	slv ( 4 downto 0 )
txPreCursor	slv ( 4 downto 0 )
txPostCursor	slv ( 4 downto 0 )

Instantiations
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_pgp3core	Pgp3Core <Entity Pgp3Core>
u_pgp3gtp7ipwrapper	Pgp3Gtp7IpWrapper <Entity Pgp3Gtp7IpWrapper>

The documentation for this design unit was generated from the following file:

Constants

Signals