Inheritance diagram for Pgp3Core:

Collaboration diagram for Pgp3Core:

Generics
TPD_G	time := 1 ns
NUM_VC_G	integer range 1 to 16 := 4
PGP_RX_ENABLE_G	boolean := true
RX_ALIGN_SLIP_WAIT_G	integer := 32
PGP_TX_ENABLE_G	boolean := true
TX_CELL_WORDS_MAX_G	integer := PGP3_DEFAULT_TX_CELL_WORDS_MAX_C
TX_MUX_MODE_G	string := " INDEXED "
TX_MUX_TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TX_MUX_TDEST_LOW_G	integer range 0 to 7 := 0
TX_MUX_ILEAVE_EN_G	boolean := true
TX_MUX_ILEAVE_ON_NOTVALID_G	boolean := true
EN_PGP_MON_G	boolean := true
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 32 := 8
AXIL_CLK_FREQ_G	real := 125 . 0E + 6

Ports
pgpTxClk	in	sl
pgpTxRst	in	sl
pgpTxIn	in	Pgp3TxInType := PGP3_TX_IN_INIT_C
pgpTxOut	out	Pgp3TxOutType
pgpTxMasters	in	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
phyTxActive	in	sl
phyTxReady	in	sl
phyTxValid	out	sl
phyTxStart	out	sl
phyTxData	out	slv ( 63 downto 0 )
phyTxHeader	out	slv ( 1 downto 0 )
pgpRxClk	in	sl
pgpRxRst	in	sl
pgpRxIn	in	Pgp3RxInType := PGP3_RX_IN_INIT_C
pgpRxOut	out	Pgp3RxOutType
pgpRxMasters	out	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpRxCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
phyRxClk	in	sl
phyRxRst	in	sl
phyRxInit	out	sl
phyRxActive	in	sl
phyRxValid	in	sl
phyRxHeader	in	slv ( 1 downto 0 )
phyRxData	in	slv ( 63 downto 0 )
phyRxStartSeq	in	sl
phyRxSlip	out	sl
loopback	out	slv ( 2 downto 0 )
txDiffCtrl	out	slv ( 4 downto 0 )
txPreCursor	out	slv ( 4 downto 0 )
txPostCursor	out	slv ( 4 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

The documentation for this design unit was generated from the following files:

Entities

Libraries