Pgp3Core.rtl Architecture Reference

Architecture >> Pgp3Core::rtl

Signals
locRxLinkReady	sl
remRxFifoCtrl	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
remRxLinkReady	sl
pgpTxInInt	Pgp3TxInType
pgpTxOutInt	Pgp3TxOutType
pgpRxInInt	Pgp3RxInType
pgpRxOutInt	Pgp3RxOutType

Instantiations
u_pgp3tx_1	Pgp3Tx <Entity Pgp3Tx>
u_pgp3rx_1	Pgp3Rx <Entity Pgp3Rx>
u_pgp3axi_1	Pgp3AxiL <Entity Pgp3AxiL>
u_pgp3tx_1	Pgp3Tx <Entity Pgp3Tx>
u_pgp3rx_1	Pgp3Rx <Entity Pgp3Rx>
u_pgp3axi_1	Pgp3AxiL <Entity Pgp3AxiL>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp3Core.vhd
• protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd