Pgp3Gtp7IpWrapper Entity Reference

Inheritance diagram for Pgp3Gtp7IpWrapper:

Collaboration diagram for Pgp3Gtp7IpWrapper:

Entities
Pgp3Gtp7IpWrapper.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
EN_DRP_G	boolean := true
RATE_G	string := " 6.25Gbps "
CLKIN_PERIOD_G	real
BANDWIDTH_G	string
CLKFBOUT_MULT_G	positive
CLKOUT0_DIVIDE_G	positive
CLKOUT1_DIVIDE_G	positive
CLKOUT2_DIVIDE_G	positive

Ports
stableClk	in	sl
stableRst	in	sl
qPllOutClk	in	slv ( 1 downto 0 )
qPllOutRefClk	in	slv ( 1 downto 0 )
qPllLock	in	slv ( 1 downto 0 )
qPllRefClkLost	in	slv ( 1 downto 0 )
qpllRst	out	slv ( 1 downto 0 )
gtTxOutClk	out	sl
gtTxPllRst	out	sl
txPllClk	in	slv ( 2 downto 0 )
txPllRst	in	slv ( 2 downto 0 )
gtTxPllLock	in	sl
gtRxP	in	sl
gtRxN	in	sl
gtTxP	out	sl
gtTxN	out	sl
rxUsrClk	out	sl
rxUsrClkRst	out	sl
rxReset	in	sl
rxResetDone	out	sl
rxValid	out	sl
rxHeader	out	slv ( 1 downto 0 )
rxData	out	slv ( 63 downto 0 )
rxSlip	in	sl
rxAligned	in	sl
rxPolarity	in	sl
txUsrClk	out	sl
txUsrClkRst	out	sl
txReset	in	sl
txResetDone	out	sl
txHeader	in	slv ( 1 downto 0 )
txData	in	slv ( 63 downto 0 )
txValid	in	sl
txReady	out	sl
txPolarity	in	sl
loopback	in	slv ( 2 downto 0 )
txDiffCtrl	in	slv ( 4 downto 0 )
txPreCursor	in	slv ( 4 downto 0 )
txPostCursor	in	slv ( 4 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd